ADS131E08: New conversion result while reading SPI packet

Hello Jeff,

Welcome to our e2e forum! 

It seems that the width of the spike pulse is small, I do not think it's a valid signal. However, I would double check. Can you please provide a closer timing for the spike for let me know how wide the high pulse of the spike is? Also, can you provide a timing plot including SCLK, /DRDY, /CS and DOUT? thanks.

Regards,

Dale

Hi Dale,

The spikes are 500ns, and they spike (falling edge) every 250us, which matches the sampling rate of 4kHz. Also, I'm currently testing on the ADC131M08EVM (our product will use the ADS131E08), so the specifics might be different.

Instead, I'm more concerned about the register behavior when new data is ready--if the new data is ready while I'm polling from the SPI, will I receive just the previous data sample (i.e. register is "locked" with previous sample), or will I get the new data for some channels and the one-cycle-old data for the others?

Hi Jeff,

ADS131M08 is quite different from the ADS131E08 ADC in terms of features and digital timing. ADS131M08 has an internal "FIFO", the "FIFO" output behavior is different when you retrieve the data in different ways. To address the issue on ADS131M08, I need more information to understand how you read the data, e.g. it seems that the data rate you configured is 4ksps, are you monitoring the /DRDY and trying to read the data after every conversion completes?

I would recommend you to directly test ADS131E08 on our ADS131E08EVM board or your own ADS131E08 circuit board since you will finally use ADS131E08 ADC in your product.

Best regards,

Dale

Thanks for the quick response, we're still waiting for our ADS131E08 board but I don't think using that board will address my question, since there's no way of telling which packet my data is from, in this scenario. The reason why we have this edge case is because we're limited to polling in arbitrary times, which might overlap with when a new data packet is ready. Does all the data update in the register at once?

Hi Jeff,

The M08 ADC has output buffer and a "FIFO" which can store two samples per channel at a time. The "FIFO" does not 100% behave as a conventional FIFO.

When the data is not retrieved from the ADC, the old data remains in the "FIFO". Depending on how you read the data, some samples could be missed and also short /DRDY high-low pulses could be seen. 

It's recommended to read the data after every conversion. 

Best regards,

Dale