ADS4449: Input Clock Jitter Requirements

How can I determine the maximum amount of jitter tolerable from my clock source? The datasheet just says to use a very low jitter clock source. I've looked at the ADC08D1520 which gives an equation to calculate maximum jitter tolerance (page 47 of the ADC08D1520 datasheet):

tJ(MAX) = ( VINFSR/ VIN(P-P)) x (1/(2(N+1) x π x fIN))

Using that equation and using parameters for the ADS4449 it seems my maximum jitter tolerance would be 77fs:

VINFSR = 2

VIN(P-P) = 2

N = 14

fIN = 125MHz

tJ(MAX) = 77fs

From reading it seems like a clock source with additional jitter would decrease SNR. How can I determine the SNR hit if using a clock source with say 150fs of jitter?