DAC8564: 2 of the 4 channels stopped responding

Hi Hamza,

Please share a schematic with all of the supply voltages and output loads clearly shown. 

There are boards with the identical setup that have worked for a while, and so far two devices on two boards with a new layout (routing) that have seen this issue? Is that right?

Can you do an A-B-A swap with one of the good boards with a good part, and one of the new boards with a part that is seeing the issue? 

Best,

Katlynne Jones 

Hi Katlynne,

Here are the schematics + an image of the routing,

Your statement is right, that is exactly my situation.

While I would try the A-B-A swap, the only old boards I have access to are unleaded soldered by a factory. With both the product theyre on being expensive and the chip itself being expensive im hesitant of potentially ruining both. I would rather try that as a last resort.

Thank you for your help Katlynne!

Hi Hamza,

We are still reviewing this.

Hi Hamza,

Can you please capture the CS, SCLK, DIN and LDAC waveform near the DAC8564 pins, just to make sure that pattern are properly coming. 

Thanks,

Sanjay

Hi Sanjay,

Just re-tested each line, the waveforms are what I would expect. LDAC is grounded through a solder jumper at the moment, I plan to eventually update the function to include it if we need more speed. 

Just to clarify, 2 of the 4 channels still respond to commands to set voltage.

Best,

Hamza 

Hi Hamza,

As i asked earlier, if you please capture the CS, SCLK, DIN and LDAC waveform on oscilloscope near the DAC8564 pins and post it here. I want check and make sure that the communication is okay and there is no violation of clock polarity, timing issue and voltage levels.

Have a great day !

Thanks,

Sanjay

Here are the screenshots from my oscilloscope. I have not shared screenshots from it before so please tell me if I need to redo them with any changes.

CS:

SCLK:

DIN:

As I mentioned the LDAC Pin is grounded, there are no transients on that trace either.

This screens are from what I believe from is refresh of the DAC voltages of all four channels being set to the same voltage. Please let me know if you need a closeup of a write to a single channel. The baud rate is set to 20 MHz

HI Hamza,

A close up of one command would be very helpful.  What we are looking for is a mismatch in the clock phase or polarity.  That is commonly the problem when you only see a subset of channels working.  It could be that the device is seeing a bit-shift and that is resulting in the command bits not being correctly latched.

This is the closest i could easily get, please let me know if it needs to be clearer, I will try again if so.

CS: (The TB is 1 us here and 500 ms for the others)

SCLK:

DIN:

Hi Hamza,

What is critical is that the data/clock relationship is correct.  Can you capture both at the same time? I recommend you reduce your clock speed as well.  From the image, it seems like the clock's line capacitance is too great or drive capability is not sufficient for that clock speed. 

I reduced speed to 2MHz from 20MHz and tried changing the polarity and phase of the SPI with no luck. Here are two screen shots of the SCLK (Top) and DIN (Bottom) line, please ignore the overshoot on the DIN line, im using a random probe and I do not have much experience with measuring high speed signals so please forgive that.

Hi Hamza,

Thanks for sharing the snapshots of the waveform.

1. Data bit (DIN) should be stable during the falling edge of the SCLK line,  not when it's rising as captured in the oscilloscope waveform. Please check the page#29 for more details.

2. Also make sure that timing parameters are being followed as per the "TIMING REQUIREMENTS" section in data-sheet.

Please make these changes and let us know if this helps to resolve your issue. 

P.S. : When device was working, it might be marginal as for DIN setup and hold times are very low. During the falling edge DIN might be randomly satisfied, but not always. 

Thanks,

Sanjay

Hi Sanjay,

For 1. I have tried changing the SCLK polarity and phase with no result, heres with the polarity flipped so that DIN is stable on the falling edge.

For 2. Im finding it difficult to verify if the timing parameters are being met but i will continue to try. If it is the issue, would a re-routing of the line with better practice fix it? I dont understand if the conditions for DIN are being randomly satisfied wouldnt the working channels also behave unexpectedly? Wouldnt changing baud rate or the order with which im writing to channels also affect it?

I will try replacing the chip today as well.

Thanks for the help so far,

Hamza

I have replaced the chip and all four channels are working, I have the older chip but it looks like it is damaged from being removed.

Will report back if channels start failing again.