ADS7881: Readout of the digitized data

Hi Dorothy,

Welcome to the E2E Community Forum!

I like your idea of saving time; however, it doesn't seem to save you much time. You could possibly use the technique you described, but you may run the risk of damaging the part or wearing it out faster over time. In your application do you need to reduce this time?

I could see where you may be concerned about sampling three things at the same time and wanting to get the results out as close as possible. Even so, because you're using a parallel data interface you are able to read out the results very fast and should have enough time to read all three outputs. It sounds like you are not trying to run the parts at maximum throughput since you are not sampling right away during the read period.

If you need to save this time then there are two things you can do to protect the part:

1. An extension of what you're already doing...increase your 10ns delay to 15 or 20ns. The output of the first device will probably have switched to a high impedance by the time the second device starts to drive the DATA bus.
2. You could add some small resistors in series with the device outputs....(yes, this may add up to a lot of resistors). The idea behind this is you are limiting the current between two device outputs in the case that one output is driving HIGH and another output is driving LOW at the same time.

Please let me know if this information helps!

Best regards,
Chris

Hi Chris,

Thanks for the prompt response.

My situation is that the board has already been built, and four of these ADS7881s are bussed together.  I have an FPGA running at about 25MHz reading them out.  So I devote one 40ns clock period to the assertion of read, and the next 40ns clock period to letting the data decay before enabling the second ADS7881 on the third clock period. And so on until all four ADCs have been read.  However, the FPGA has very slow I/O specifications and I'm having trouble turning around the data in 40ns.

So my proposed solution is to assert read for 1.5 clock cycles and deassert it for 0.5 clock cycles.  This would give me 20ns of decay time.  The reason I said 10ns in my original question was that I wanted to test the boundaries.  However, it will really be 20ns if everything is perfect (50% clock duty cycle, and 0ns skew between I/O buffers).  Realistically, it will probably be 15ns worst case between any adjacent assertions of the READ strobes.

There are already series resistors on all the data lines.  We put these in-line to control ringing, but on the other hand, I cannot afford to slow down the interface too much.  Do you think a 20 ohm series termination would keep the current limited sufficiently, considering that the read strobe assertion would be guaranteed a 15ns separation?

Dorothy

Hi Dorothy,

I working to get some more information from the designer regarding the amount of current the digital outputs on the ADS7881 are able to source and sink safely and what the internal protection circuitry is able to handle. I am also trying to see if perhaps there is a typical value for td9 that is much faster than 25ns.

Are the series resistors on the data bus shared for all the devices on the bus or are they used between each of the ADC7881 outputs? See the image below....

In the first case, the series resistor provides no protection for currents between devices while the second case does, but requires many more resistors. For the second case, if you had two 20 Ohm resistors between devices then for +VBD = 3.3V the current could not exceed 82.5mA but the drive capability of the sourcing ADC and the output impedance of the sinking ADC would also limit this current. Being unfamiliar with TTL logic currents I don't know if this will damage the part but I will try to find out.

Regards,
Chris

Dorothy,

 I also meant to ask you:

• What is your sampling rate and are you trying to get maximum throughput out of each ADS7881?
• Are you trying to get simultaneous sampling where each part captures data at the same time?
• How are your digital inputs configured? Are you using a bus for the /CONVST and /RD or do all the parts have there own inputs that you can configure separately?

Regards,
Chris

Hi Chris,

We are sampling at about 2.5MHz (must read the four ADCs every 400ns).  I'm using the pipelined nature of the devices a little bit, but am not pushing them to their maximum throughput (which I cannot really accomplish with the bussed nature of the connection).

Each part does capture data at the same time.  Although CONVST and RD are as separate signals, they are asserted at exactly the same time for the group of four ADCs.

To answer your earlier post:  unfortunately, the series resistors are configured as one per data line (i.e. the four ADC data lines are connected).  So there's no protection from double-driving the databus signals.  However, if I wait ~20ns -- does this cause a problem?  Would the ADC outputs be compromised or damaged?

Dorothy

Waiting 20ns will most likely be enough time for the device to go into tri-state. The datasheet only gives a max value of 25ns but I  suspect that the typical time is 20ns or less.

I don't think you will damage the devices; however, I am still waiting to hear from the designer.

Regards,
Chris

Hi Chris,

This is very useful information.  If I can start the READ for the n+1 device while the nth device is still "decaying", this gives a much needed increase in my ADC Read Cycle margin.

Thanks for all your assistance.

Dorothy