ADS4149: jitter and skew requirement for input clock

Chi Zhang2

Part Number: ADS4149

Hi expert,

my customer want to use ADS4149 in fixed network ODU, but there is no spec for input clock clkp/n. could you help to check

jitter or phase noise requirement for clkp/n

Chi

over 1 year ago

0 Chi Zhang2 over 1 year ago

TI__Intellectual 2550 points

Hi expert,

in the datasheet, there is clock gen inside our ADS4149, and datasheet highlight input clock need very low jitter with high sampling rate, so do we have a specific requirement? thanks.

Chi

0 Chase W over 1 year ago in reply to Chi Zhang2

TI__Mastermind 22950 points

Hi Chi,

To achieve datasheet performance metrics of this device the lowest jitter clocking source should be used. Please find the below articles useful. In particular, the first part contains the equations you will be interested in which show the degradation of SNR as a result of clock jitter.

Clock jitter analyzed in the time domain, Pt. 1
Clock jitter analyzed in the time domain, Pt. 2
Clock jitter analyzed in the time domain, Pt. 3

Regards, Chase

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ADS4149: jitter and skew requirement for input clock