TI-JESD204-IP: Simulation of loopback design in Vivado

Hi Etienne,

After checking with out team I have found that the below edits are required in order to use the top level file as the testbench. Can you confirm that you have followed these on your project?

You will be able to use the top level file reference design (TI_204c_IP_ref) as the testbench. Kindly follow the steps below:

• File edits:
  • Connect the dac_lane_txp/n signals to adc_lane_rxp/n (loop back data)
  • Connect the cc_sysref_out_p/n signals to the sysref_p/n signals (loop back an internally generated SYSREF). Alternatively, you can force your own sysref frequency on sysref_p/n.
  • Connect the adc_rx_sync_n to the dac_tx_sync_n (if you are using an 8b/10b mode)
  • Disconnect the following outputs of the VIO module in the reference design, so you can force them directly:
    • master_reset_n
    • rx_sync_reset_vio (becomes the rx_sync_reset of the JESD IP)
    • tx_sync_reset_vio (becomes the tx_sync_reset of the JESD IP)
• Simulation steps
  • Force a clock of 156.25MHz on the refclk_p/n ports (reference clock to the transceiver)
  • Force a clock of 156.25Mhz on the sys_clk_p/n ports (reference clock to the PLL in the reference design)
  • Force master_reset_n to ‘0’, and tx_sync_reset_vio and rx_sync_reset_vio to ‘1’
  • Run for 100ns
  • Force master_reset_n to ‘1’
  • Run for a few us, until you see the QPLL0 lock signals transition to ‘1’ (indicating that transceiver PLLs have locked)
  • Force tx_sync_reset_vio to ‘0’. This will start the Tx part of the JESD IP
  • Run for a couple of us
  • Force the rx_sync_reset_vio to ‘0’. This will start the Rx part and it will lock onto the Tx.
• You should now be able to monitor rx_lane_data and tx_lane_data signals of the IP to see that the same values are being looped back
  • You can also check the sample values in the refdesign_rx and refdesign_tx submodules