• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 46 subscribers
  • Views 195 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC3441: Synchronization issues

zhang ping
Genius 3445 points
Part Number: ADC3441

Are the sampling of the 4 channels synchronized? From this timing chart, does the output data appear to be out of sync? Latency=8 x CLKIN Cycles+tPDI - tA, what does this delay time refer to?

  • 0
    TI__Genius 13301 points

    Hi Zhang,

    The sampling of the 4 channels is synchronized. If you look at the timing diagram in the datasheet that is in the middle of Figure 141, you can see that for one cycle of the FCLK a single data sample is captured. ADC latency is the time that it takes the device to sampling the input signal and convert it to a digital binary word at the output. The equation for latency, as you mentioned -> Latency=8 x CLKIN Cycles+tPDI - tA, describes the latency for the entire chip. Several factors contribute to latency, i.e., tPDI (clock propagation delay); tA (aperture delay). 

    Regards, Amy

  • 0 in reply to Amy
    Genius 3445 points

    Can ADC3441 support a 10M sampling rate? The minimum setting is 15M（Table 20）, how to set 10m?

  • 0 in reply to zhang ping
    TI__Genius 13301 points

    Hi Zhang,

    The ADC3441 has a minimum sampling rate of 15M, this cannot be lowered.

    Regards, Amy