Hello E2E Experts,
Good day.
I have a technical question regarding the input signal of the ADS54J60EVM ADC of the TI.
I try to digitalize a signal that every 100 μs presents a peak that has a frequency of 80 MHz duration of approximately 400 ns and Vpp of approximately 4.4 V (-2.2V to 2.2 V). The Vpp could be 2 or three times higher in some cases. At this moment I am using a voltage divider to bring the signal down to Vpp ~1V but this reduce also the signal between the peaks and I would prefer not to do this.
Can you propose me a different approach?
In addition, I need to leave the input signal unchanged except for the initial part of approximately 400 ns where the signal should be limited, but not attenuated, to not exceed the ADC FSR.
Regards,
CSC
