ADS9817: Effective bit and output order

David Park

Part Number: ADS9817

Hi,

There are 2 questions.

1. what is MSB/LSB for effective 18bit of 24bit output? it seems to be D23~D6. is it correct?

2. Somtimes Ch2 or Ch3 data outputs firstly instead of Ch1 data on D3 and D2 line after rising of FCLKOUT. it's same on D1 and D0 as well. do you have any troubleshooting guide or experience like this?

operating condition:

it's for 4-SDO DDR CMOS Data interface.

24bit output after demuxing from 1 ch to 2 SDO line

Thanks.

over 2 years ago

0 Tom Hendrick over 2 years ago

TI__Guru**** 179731 points

Hi David,

For Q1 above - yes, that is correct. For Q2, I've not heard of any issues where CH2 or CH3 data come out ahead of CH1.

0 RahulVK over 2 years ago

TI__Expert 3785 points

Hi David,

The output data from the ADS9817 is MSB aligned. In a 24-bit output packet, bits [23:6] are ADC data.
The host must provide a SYNC pulse on the SMPL_SYNC pin on power-up. This ensures that the ADC outputs CH1 and CH8 data on FCLKOUT rising edge. The seuence of channel data is undetermined if SYNC pulse is not used.

Regards,

Rahul

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ADS9817: Effective bit and output order