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TLV2544: Designing with TLV2544

Shibin Varghese
Intellectual 835 points
Part Number: TLV2544

Hello Team,
We are planning to use the ADC TLV2544 for one of our applications.
The ADC will be sampling at a rate of 200ksps.
What will be the total latency of the ADC?

What is the throughput of the ADC?
Based on a rough calculation, I assume
200ksps means
Acquisition time (Sampling time) is 5us.
The conversion time is 3.86us.
So the total time taken will be 5+3.86=8.86us.
For 8 channels, the time will be 8*8.86us = 70.88us.
This means the FIFO will be filled in every 70.8us.
So I need to read the FIFO (12*8 = 96bit) in every 70.88us.
Please correct me if I am wrong.
Also, I have 6*ADC in the same SPI of the controller.
We have to read all ADC channels (6*8) within 2ms.

Looking for your reply.

  • 0
    TI__Guru**** 177701 points

    Hi Shibin,

    The TLV2544 throughput is MAX 200kSPS, so that is 5uS total time for conversion and acquisition.  The conversion time (t(conv)) is listed on page 24 - assuming you use the internal oscillator, it is 3.5uS.  The acquisition time is adjustable, but to maintain the 200kSPS rate, it is 600nS.  For 8 channels you have 8*5uS or 40uS in total.  You should be able to read out 8 channels from 6 devices in under 2mS.

  • 0 in reply to Tom Hendrick
    Intellectual 835 points

    Hello Tom,

    Thank you for your reply.

    The total ADC latency is the sum of acquisition time and conversion time.

    So must be 5+3.86=8.86us.

    Please correct me if I am wrong.

    We only have a single SH circuit in the IC.

    Or is the 200ksps in the data sheet the digital throughout through SPI?

    If we don't need to consider the conversion time, can you please explain the relevance of the conversion time of an ADC?

  • 0 in reply to Shibin Varghese
    Intellectual 835 points

    Hello Tom,

    Thank you for your time.

    The 200ksps represented in the datasheet was the throughput of the ADC.

    For 200ksps throughput, what will be the sampling rate of the ADC?. Or both sampling rate and throughout the same?

    I hope both settling time and conversion time are included in it.

    So 200ksps means 5us ADC latency.

    Can you please explain why the latency is not 600ns + 3.83us (acquisition time + conversion time).

    Or is there any parameter I'm missing!

  • 0 in reply to Shibin Varghese
    TI__Guru**** 177701 points

    Hi Shibin,

    Sample rate and throughput are the same thing.  The TLV2544 can sample one channel at 200kSPS, two channels at 100kSPS/CH or four channels at 50kSPS/CH.  So eight channels (2 pieces of the TLV2544) would take at least 40uS, plus some headroom for switching between parts, to get all conversion results when sharing a single SPI bus.  Six devices at 5uS/CH would be ~120uS.

    The TLV2544 is a successive approximation register (SAR) converter.  SAR converters don't normally consider 'latency' to be an issue since there is only one 'sample' for each conversion result.  That being said, the TLV2544 does output conversion result N-1 while it is sampling conversion 'N', which could be looked at as latency.  If you are using the FIFO, you would be storing up to eight samples and reading them all out back-to-back.

  • 0 in reply to Tom Hendrick
    Prodigy 140 points

    Hello Tom,

    Is there any specific mode required to acheive this condition?

    Or can we achieve this in any mode?

  • 0 in reply to Alan Varghese
    TI__Guru**** 177701 points

    All modes listed in Table 4 with normal sampling can achieve this.