ADC12DJ3200EVM: ADC12DJ3200 not interopable with FPGA at high data rate

Any clue on this ? Please let me know

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Hi TI E2E support forums

Can you please look into this?

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Hi Neeraj Gill

Sorry for the delayed response. I have taken care of your above suggestions but still the issue remains same.

To dwell deeper into this, as soon as I program my FPGA and program my ADC card, the link is well established with ADC register 0x208, reads '64'. But as soon as I reset the FPGA design, the link goes down and I see disparity and code violation errors. My SYNC signal stays low after that and never goes low.

Same FPGA design works fine for 5 Gbps but not sure whats happening with 10Gbps. Why SYNC never goes high after reset? Any idea? Any specific registers I need to configure in ADC GUI, my Fs=2500 Msps and I am using JMODE2. 

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Hi Neeraj Gill

Here is the register write to the adc card, in case you want to check8078.register_write.cfg

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Hi Neeraj Gill

Sure, will try your suggestions. Please suggest below:

>>To dwell deeper into this, as soon as I program my FPGA and program my ADC card, the link is well established with ADC register 0x208, reads '64'

Above is happening when i am supplying fpga clock from the on board oscillator . But when I try to send clock from ADC evm oscillator clock never reaches FPGA for 10Gbps. What I am doing wrong here? Any pointers which I can look for . 

For 10 Gbps, my Fs=2500, JMODE2 in the ADC GUI. (clock not coming up)

for 5 Gbps, Fs=1250, JMODE2 in the ADC GUI ...this works fine always, link is well established with good clock from ADC.

Awaiting your response.

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Hi Neeraj Gill

I don't think this isa  signal integrity issue as i tried changing both my FPGA board and ADC card and the issue stays the same. SYNC never comes up. 

I have set Fs=2500 and my LMK value is set to 10. Please see the screenshot below:

On FPGA side, I have set reference clock of transceiver as 250 MHz while my data rate is 10 Gbps. JESD IP connected to XCVR uses 125 Mhz clock= 10Gbps/64=125 Mhz. 64- bit because width to fabric(jesd) from Transceiver is 64 bit. I am not sure what I am doing wrong here. Same design at 5Gbps works so consistent.

Please suggest.

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Hi Neeraj Gill

125 Mhz to my JESD Rx is recovered/ parallel clock from the Transceiver. 

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Unlocked

Hello,

Can you clarify I am not exactly sure what you mean by the clock is recovered from the transceiver, if you are using the EVM the ref clock should be coming from the EVM.

Thanks,

Eric