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ADC128S102: ADC128S input resistance

Flavio
Prodigy 20 points
Part Number: ADC128S102

Hi there,

I am using the ADC128S102WGRQV. In the part datasheet in section 7.3.2 it is recommended to keep the input resistance to <100 Ohm. However with such a low external resistor value we won't be able to limit the ADC internal ESD diode current to less than 10mA (our ADC driver output voltage can exceed the ADC Vref).
So I need to increase the size of the external input resistor to more than 100 Ohm and so if possible I would like a clarification on the 100 Ohm recommendation. I am trying to find more info on that recommendation.

From the datasheet section 7.4.1 I understand that the track mode lasts for 3 clock cycles and the other side of the sampling capacitor is Vref/2. The sampling capacitor is 30pF (section 7.3.2) and Rmux about 500Ohm.

From my view, please let me know if correct: as long the RC formed by the external input resistance (+Rmux) charges the sampling capacitor (30pF) to within 1 LSB of the max input voltage in the 3 clock cycles, then the input resistance makes no difference (as Csample is charged).  In other words: is it true I can make Rinput as big as I like as long as I consider the charging time  in 3 clock cycle?

As an example:
given that the ADC max clock frequency is 16MHz, the ADC minimum sampling time would be 187ns (3 clk).
Assuming Vref=5V, then the maximum voltage on sampling capacitor is 2.5V. Even with Rext=300Ohm (800 Ohm total including Rmux) the sampling capacitor is charged to within 1LSB of 2.5V in 187ns.
So I am not too sure where the 100Ohm recommendation comes from.

Also note: by putting a capacitor at the input I have extra charge that is only limited by Rmux, so the calculations above are conservative because the assume all the charge needed to charge the sampling capacitor comes from the ADC driver.


Does anybody know Is there something else I should taking into account? Or can I increase the external input resistance as long as I make sure the Csampling is fully charged (within 1LSB) during the sampling phase?

  • +1
    TI__Expert 6811 points

    Hi Flavio,

    Thank you for your question! The sampling capacitor actually needs to be charged within 1/2 LSB of the maximum input voltage. This video gives a good overview on the math behind RC values (link). But to answer your question, yes, as long as the sampling capacitor is fully charged within 1/2 LSB within the acquisition (track) time, it should be fine.

    Regarding the ADC output voltage exceeding the reference/analog supply voltage, we recommend avoiding this case if possible. As shown in Figure 38 in the datasheet section 8.2, if a driver is not used to limit the maximum input voltage and source impedance, a Schottky diode can also be used to clamp the voltage:

    I hope this helps!

    Best regards,

    Samiha

  • +1 in reply to Flavio
    TI__Expert 6811 points

    Hi Flavio,

    Thanks for your response! The internal sampling capacitor doesn't discharge between samples. When SW1 is connected to ground, the sampled voltage is maintained. I believe the comparator uses VA/2 (or Vref/2) as a comparison value to help translate the sampled voltage to a conversion result.

    The external resistor <100ohm recommendation may be explained by using the Analog Engineer's Calculator, which helps us calculate the approximate RC filter values to ensure the sampling capacitor settles within 1/2 LSB during the acquisition period.

     

    The charge droop you are seeing is probably from both the input capacitor (470pF) and the sampling capacitor (30pF) which are being charged for every sample. An approximation of the droop you should see is (30pF/470pF) = 6.38%. As your input is 2.5V, 6.38% of 2.5V is 159.57mV, which is similar to the droop you see, so I believe this is expected.

    However, the 10kohm resistor in series is causing your sampling capacitor to take over 5us to charge. However, the acquisition time (when SCLK is 16MHz) is 187ns, so the sampling capacitor will not settle to the correct value within 1/2 LSB before the conversion begins. Thus, such a large resistor in series may cause errors in your conversion results. Are you seeing any errors in your results currently?

    These videos may help better explain what is happening during SAR sampling and how a large external resistor affects the ADC: 

    I hope that helps!

    Best,

    Samiha