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DAC38J82: The internal PLL is not working properly

Part Number: DAC38J82

Hi team,

The DAC works without the internal phase-locked loop. The sample clock cannot be generated using the internal PLL, read config108 0x0003. Input clock is 250M and it's required to generate 1GHz sampling clock. 

The following register configurations are generated using the GUI:

0x00 0x0218
0x01 0x0000
0x02 0x2082
0x03 0xF081
0x04 0x00FF
0x05 0xFF0D
0x06 0xFFFF
0x07 0x0000
0x08 0x0000
0x09 0x0000
0x0A 0x0000
0x0B 0x0000
0x0C 0x0400
0x0D 0x0400
0x0E 0x0400
0x0F 0x0400
0x10 0x0000
0x11 0x0000
0x12 0x0000
0x13 0x0000
0x14 0x0000
0x15 0x0000
0x16 0x0000
0x17 0x0000
0x18 0x0000
0x19 0x0000
0x1A 0x0000
0x1B 0x8000
0x1E 0x1111
0x1F 0x1140
0x20 0x0000
0x22 0x1B1B
0x23 0x010A
0x24 0x0000
0x25 0x0000
0x26 0x0000
0x2D 0x0000
0x2E 0xFFFF
0x2F 0x0000
0x30 0x0000
0x31 0x6408
0x32 0x0730
0x33 0x4DFC
0x34 0x0000
0x3B 0x8800
0x3C 0x0028
0x3D 0x008F
0x3E 0x0128
0x3F 0x0000
0x46 0x0044
0x47 0x190A
0x48 0x31C3
0x49 0x0000
0x4A 0xFF21
0x4B 0x1F00
0x4C 0x1F07
0x4D 0x0101
0x4E 0x0F0F
0x4F 0x1CC1
0x50 0x0000
0x51 0x00FF
0x52 0x00FF
0x53 0x0000
0x54 0x00FF
0x55 0x00FF
0x56 0x0000
0x57 0x00FF
0x58 0x00FF
0x59 0x0000
0x5A 0x00FF
0x5B 0x00FF
0x5C 0x1101
0x5E 0x0000
0x5F 0x0123
0x60 0x4567
0x61 0x0003
0x64 0x0000
0x65 0x0000
0x66 0x0000
0x67 0x0000
0x68 0x0000
0x69 0x0000
0x6A 0x0000
0x6B 0x0000
0x6C 0x0000
0x6D 0x0000
0x6E 0x0000
0x6F 0x0000
0x70 0x0000
0x71 0x0000
0x72 0x0000
0x73 0x0000
0x74 0x0000
0x75 0x0000
0x76 0x0000
0x77 0x0000
0x78 0x0000
0x79 0x0000
0x7A 0x0000
0x7B 0x0000
0x7C 0x0000
0x7D 0x0000

Could you help check this case? Thanks.

Best Regards,