ADC128S102: Rise time limits

Hi Samiha, can you clarify what you mean by 'too high'? Does that mean when the input rise time is too long or too short? I would expect based on your description that too fast a rise time at the input would cause ringing at the output, is that correct?

Hi Courtney,

I was referring to the SCLK input rise time being too sharp, which may cause ringing. Is that what you were asking about?

Yep, thank you for clarifying! Do you have an estimate for where this becomes a concern for this device? Should the input rise/fall times be over 100ps, or over 10ns (for example)? 

Hi Courtney,

Unfortunately, I don't have any estimates for these times.

Best,

Samiha

I did some further analysis based on the clock frequency and the SCLK high/low times. Can you confirm that this analysis correctly identifies a maximum limit for the rise and fall times?

Assuming tSCLK = tCH + tFALL + tCL + tRISE

From datasheet, page 7: tCH = tCL = 0.4*tSCLK (Minimum)

Therefore tRISE + tFALL = 0.2*tSCLK (Maximum)

Assuming tRISE = tFALL

tRISE = 0.1*tSCLK (Maximum)

Thus with an example clock speed of 16MHz, the rise/fall times could not be greater than 6.25ns. Slower clock speeds would allow longer rise times.