DAC39J84EVM: Query regarding maximum sample rate achievable and its relation with the clock

Hi Vaibhav,

Vaibhav Jain said:

1) Are the external clock frequency  provided ( say 1GHz ) and DAC data input rate field on the DAC GUI same things when operating in external Clock mode ? Also, is DAC data output rate field similar to the DAC sampling rate. Basically, I wanted to know how are the DAC sampling rate and the external clock provided is related ? A simple example to understand these might be really helpful. 

If the DAC is operating without any interpolation, then the external clock frequency will match the DAC input data rate. The DAC input data rate will refer to the speed at which samples will be fed into the DAC. On HSDC Pro, the Data Rate field represents the FPGA output data rate which will feed into the DAC. These speeds must match or else the FPGA will try to send data at a rate different than what the DAC is expecting and the link will not come up. The DAC sample rate WILL match what the externally provided clock is. In some devices, such as DAC38RF82, there is an internal PLL which can be used to sample the DAC38RF82 at 9GSPS while only provided with a reference frequency in the hundredths of MHz range. For this DAC39J84, the external clock must match the DAC output data rate.

Vaibhav Jain said:

2) Assuming the external clock is related to the DAC sampling rate, it seems the maximum DAC data input rate or the clocking frequency we can go with is 1.25 GSps (or 1.25 GHz) owing to the maximum SerDes Linerate limit and the maximum DAC Output rate limit. As, the maximum sampling rate is 2.8 GSps for this DAC, the maximum we can achieve using these settings seems like a DAC data output rate of 2.5 GSps ( setting interpolation 2 and Ser Des lanes as 8) ( screenshot attached) . Is that the maximum we can achieve and not 2.8 GSps? If yes, how can we achieve the stated 2.8 GSps sampling rate?

With interpolation set to 2, the max sample rate this DAC supports will be 1250MSPS or else SerDes will operate too fast for this device. To achieve faster sample rates, you must use a higher interpolation factor, which will directly relate to a reduction in input data rate and bandwidth. There are a few rules to follow here.

     1. Serdes rate must be valid (<12.5Gbps)
     2. The DAC sample rate must be valid (<= 2.8GSPS)
     3. The input data rate (DAC incoming data rate = FPGA outgoing data rate) must match DAC Sample Rate / Interpolation factor
     4. The available bandwidth will be directly related to the response of the interpolation FIR filter. As you increase interpolation factor by 2^N, the bandwidth will be reduced by a             factor of N.

An example to achieve the maximum bandwidth available while sampling at 2.8GSPS would be: 4x Interpolation, 700 MSPS input data rate (700MSPS * 4x interpolation = 2800MSPS DAC output rate), Serdes will be 7Gbps, bandwidth will be Fs / (2 * 4) = 2800 / 8 = 350MHz IBW.

Vaibhav Jain said:

3) Another thing I wanted to understand is why the bandwidth of DAC is half of the DAC data output rate or the sampling rate and how are they related (For example if we take an external clock of 1 GHz, so DAC data input/output rate is 1 GSps, assuming interpolation as 1. Then when we enter data rate as 1GHz on HSDC Pro software, we get the bandwidth of DAC as 500 M on the FFT diagram ( screenshot attached))  ?  Do I need to change some settings to access full bandwidth as the external clock provided?

This is all sampling theorem. In order to retain information, you must follow sampling theorem. In this case, with sampling rate at 1GSPS, the Nyquist zone will be Fs/2 = 500MHz. This is often referred to as the instantaneous bandwidth, or IBW. You cannot achieve a bandwidth greater than the Nyquist frequency. As you add interpolation factors, the input data in padded with zeros and the resulting stream of data passes into an interpolation filter, composed of an FIR filter. This filter reduces the bandwidth of the output by another factor of N for every 2^N of interpolation. Interpolation adds latency inherently due to the use case of an FIR filter. Interpolation is also used for frequency planning to help push images out of band.

For example, the bandwidth for 1GSPS operation without interpolation is 500MHz. If you interpolate by 2, this is reduced to 250MHz. If interpolating by 4, the bandwidth is reduced to 125MHz, and so forth.

Regards, Chase