AFE5851: AFE5851 - sampling two AFE5851 data with ones bit clock

Hi Gergely,

Thanks for reaching out to TI.

The delay between the adc clock and the output interface clock (i.e fclk or dclk) is not fixed and can have variation across devices. Table 1 Output Interface Timing also shows the same.

Hence it is not a good idea to use 1 DCLK for other devices. It may be possible that in some devices the timing (setup and hold) fails. However, if you are doing DPA (dynamic phase alignment) inside the FPGA for all the channels by training. You can use 1 device DCLK to align the data across multiple channels as well as devices.

Thanks & regads,

Abhishek

As far as I can see Table 1 Output Interface Timing (the one below) does not show the variation: the column of tpdi MIN and MAX are empty. I can only deduce the variation of tpdi from the variation of tdelay. But it is unclear what the 2 lines for tdelay in the table above really mean. Specifically: how should I understand 'At fixed supply and 20°C T difference'? If the power supply is constant over time, but the temperature changes 20°C, then the tdelay will change between -1 and 1 ns (no typical value for this), but if they're constant, tdelay is also constant?
And in https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/369089/forcing-afe5851-frame-clock-phase I read: "Per the datasheet specs, the frame clock across multiple devices will be 'synchronized' (within a window of 6.4ns-3ns=3.4ns) so long as the input clocks to the multiple devices are very closely aligned."
From this I understand, that none of these 2 variances will cause the change of tpdi after startup if the temperature and the power supply is constant.
So let's say after both ADC reaches their final temperature, at 20MHz sampling rate ADC_0 has tdelay=3.7 ns => tpdi_0=12.5 + 3.7 = 16.2 ns, and ADC_1 has tdelay=5.7 ns => tpdi_0=12.5 + 5.7 = 18.2 ns. And this stays the same as long as the temp, and power supply is unchanged. Am I right here?

Hi Gergely,

I will get back to you on this by tomorrow as I am out of office.

Thanks & regards,

Abhishek

Hi Gergely,

Sorry for the delay in response and thanks for your patience.

I am consulting with the design team on this one, to provide you the right information with data. 

Kindly allow me some more time to get the required information.

Regards,

Abhishek

Hi Abishek,
Thank you for the leg-work, I still have time to figure this out, so it's fine.
BR,
Gergely

Hi Gergerly,

Thanks for the patience.

The people from the design team are out of office hence it is taking some time to get the information.

Please be assured that I am keeping an eye on this one and shall let you know the answer soon.

Thanks & regards,

Abhishek

Hi Abhishek!
Do you have any updates on this one?

Hi Gergely,

Thanks for your patience.

I checked with the design team about your query. Here is the response from them.

Your understanding about min/max variation of Tpdi is correct. Datasheet mention that the variation is +/-1ns and it covers variation across temperature and devices but we don't have break up details like how much delay is varying due to temperature and how much across devices. We think you can use one bit clock to de-serialize the data of other devices since LVDS speed is not high but have an option of dynamic phase alignment in FPGA to make it robust in production.

Thanks & regards,

Abhishek