Other Parts Discussed in Thread: ADC08DJ3200
Hi everyone!
We have a project where we want to connect an ADC08DJ3200 to an Artix7 FPGA. An other team has begun making the final board with the correct FPGA and the ADC but in the mean time I would like to be able to begin testing part of the FPGA firmware. For that I have the AC701 board from Xilinx. I've already been able to find a loopback card that will probably work but I'm now wondering if it would be possible to connect the ADC08DJ3200EVM directly using a FMC+ to FMC connector. Of course I would not have the full bandwidth or number of lane, but that will be improved upon in our final custom board. The problem comes were in the AC701 board, only 2 lanes are connected to the GTP transceiver on the FPGA and if I look in the datasheet of the ADC08DJ3200, there doesn't seem to be a JMODE for only two lanes. The other problem is that the lane connected to the FPGA would be the DA1 pair and the DA3 pair of the JESD204 connection.
So here's my question: What would happen if I put the ADC in a JMODE with more lane (If I use 4 lanes, all the lane going to the FPGA would be used) and programmed the FPGA to get 2 lanes, would it work? What would happen to the unconnected lanes, would they interfere with the other signal or is that not advised for the well being of the ADC? I'm guessing that if I do that I would be getting 2 out of 4 data per clock cycle which is suitable to just begin testing.
If you have any other insight, I would really appreciate it.
Regards,
Étienne
