ADC12DJ5200RF: from ADC12DJ3200 to ADC12DJ5200

Amy Luo

Part Number: ADC12DJ5200RF
Other Parts Discussed in Thread: ADC12DJ3200

Hi team，

One of our customer's issues,, could you please provide some troubleshooting suggestions

Hello, we have completed debugging ADC12DJ3200 recently. Now we are starting to debug the ADC12DJ5200, and their circuits are completely consistent.

Firstly, we use a single channel 10G sampling with the following settings:

ADC12DJ5200 uses JMODE1 mode, K=4

JESD_ CORE_ CLK=250MHZ

Refclk=250MHZ

ADC_ SYSREF_ CLK=FPGA_ SYSREF_ CLK=31.25MHZ

Using the Transport Layer test mode, it was found that the received data will have periodic errors, as shown in the image of data intercepted by ILA, and the red marked points indicate the erroneous data.

Next, we try 9.8G sampling and set it as follows:

ADC12DJ5200 uses JMODE1 mode, K=4

JESD_ CORE_ CLK=245MHZ

Refclk=245MHZ

ADC_ SYSREF_ CLK=FPGA_ SYSREF_ CLK=30.625MHZ

Using the Transport Layer test mode, it was also found that the received data may have periodic errors, but the error points are different from when sampling 10G. The figure shows the data intercepted by ILA, and the red marked points indicate the error data.

Next, we use 8G sampling and set it as follows:

ADC12DJ5200 uses JMODE1 mode, K=4

JESD_ CORE_ CLK=200MHZ

Refclk=200MHZ

ADC_ SYSREF_ CLK=FPGA_ SYSREF_ CLK=25MHZ

The operation is normal in this mode,

May I ask what may be the reason?

Best Regards,

Amy Luo

over 1 year ago

0 Rob Reeder over 1 year ago

TI__Mastermind 24420 points

Hi Amy,

Is this using our EVM and data capture board? or is this the customer own board design they are finding the issues on?

Thanks,

Rob

0 Amy Luo over 1 year ago in reply to Rob Reeder

TI__Expert 6895 points

Hi Rob,

Thanks for looking into. The customer used their own designed board, with the ADC12DJ3200 and ADC12DJ5200 designs identical, only replacing ADC12DJ3200 with ADC12DJ5200 on the original board. Moreover, the 8G sampling of the ADC12DJ5200 board has been debugged successfully, and the 10G sampling encountered the above issues.

0 Neeraj Gill over 1 year ago in reply to Amy Luo

TI__Mastermind 20541 points

Hi Amy,

To me this looks like signal integrity issue. The customer can play with Pre-emphasis setting on the ADC side for serdes.

By programming the register address 0x48 with value of 0x01 or 0x02,0x03 and so on and see if the issue goes away.

On the FPGA side they can play with equalization setting and see if it helps with the issue.

Regards,

Neeraj

0 Amy Luo over 1 year ago in reply to Neeraj Gill

TI__Expert 6895 points

Hi Neeraj,

Glad to see your reply. Please find below feedback.

According to your suggestion, we have modified the code and it is currently running normally in test mode 5, as shown in the figure:

But if ADC is set to normal sampling mode, the SYNC signal will occasionally be pulled down, as shown in the figure. How can I solve this problem? Thank you.

Best Regards,

Amy Luo

0 Neeraj Gill over 1 year ago in reply to Amy Luo

TI__Mastermind 20541 points

Hi Amy,

If the problem was solved when by changing the pre-emphasis settings it confirms signal integrity issue. Was equalization setting on the FPGA also adjusted?

If not i would suggest sweep pre-emphasis setting vs equalization on the FPGA for all the option and see which settings works.

if you don't get a stable setting on the ADC and FPGA side. Otherwise the other option would be to re do the board with signal integrity in mind.

Regards,

Neeraj

0 Amy Luo over 1 year ago in reply to Neeraj Gill

TI__Expert 6895 points

Hi Neeraj,

Sorry for re-open the thread, but the customer inquired about the following questions

At present, we use 10G sampling to sample a 50MHZ sine clock, and the waveform obtained is as follows. May I ask what may be the problem? Thank you very much for your patient answer.

There are 160 points in the sampling data output of the two sub ADCs in the ADC, which are periodic and have data mutations,

And the sampling data of the two sub ADCs at the same time differ greatly, making it impossible to perform data cross integration.

Best Regards,

Amy

0 Amy Luo over 1 year ago in reply to Neeraj Gill

TI__Expert 6895 points

Hi Neeraj,

update from the customer:

This is our sampling of triangular waves. From the details, there are still fractures at every 160 points sampled, as shown in the following figure:

The figure shows a part of the triangular wave.

Would you spare some time to give customers some troubleshooting suggestions?

Thanks,

Amy

0 Amy Luo over 1 year ago in reply to Neeraj Gill

TI__Expert 6895 points

Hi Neeraj,

Could the above phenomena of the customer also be caused by signal integrity issue?

Regards,

Amy

0 Neeraj Gill over 1 year ago in reply to Amy Luo

TI__Mastermind 20541 points

Hi Amy,

The pattern is displaying jumps which getting repeated periodically. Based on this phenomenal we can eliminate the signal integrity theory. Looking at the latest pattern of triangle wave, The issue seems to be in transport layer.( How samples are collected from JESD lanes and channelized). Can you ask customer to try the transport layer test pattern and check if the output pattern from transport layer is as expected.

Regards,

Neeraj

0 Amy Luo over 1 year ago in reply to Neeraj Gill

TI__Expert 6895 points

Hi Neeraj,

Thanks for taking the time to respond, really appreciated!

Here's what I've received from customer:

This is the data we obtained using the transport layer testing mode, and there should be no problem.

Regards,

Amy

0 Neeraj Gill over 1 year ago in reply to Amy Luo

TI__Mastermind 20541 points

Hi Amy,

If the transport layer pattern test looks ok then the issue might be in converting the lane data into samples.

Regards,

Neeraj

0 Amy Luo over 1 year ago in reply to Neeraj Gill

TI__Expert 6895 points

Hi Neeraj,

Could you provide your suggestions on the following related issue

Convert the 256-bit channel data output by the JESD IP core of FPGA into sample points. This module was written by ourselves and runs normally in 8G sampling mode. If converting to 10G sampling mode is not normal, what may be the problem?

Thanks,

Amy

0 Amy Luo over 1 year ago in reply to Amy Luo

TI__Expert 6895 points

Sorry for pushed, any update on here?

0 Eric Kleckner over 1 year ago in reply to Amy Luo

TI__Expert 3900 points

Hi Amy,

Sorry for the delayed response, I am working on getting you an answer if you could give me till Friday I will get back to you on this.

Thanks,

Eric Kleckner

0 Eric Kleckner over 1 year ago in reply to Amy Luo

TI__Expert 3900 points

Hi Amy,

Could you expand on the problem you are having a bit more. I am not exactly sure what you are trying to do.

Thanks,

Eric Kleckner

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ADC12DJ5200RF: from ADC12DJ3200 to ADC12DJ5200