This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC32J25: ADC JESD can't link with the receiver FPGA

Part Number: ADC32J25

Hello

    I am bringup a demodulator which need to use ADC to convert the data to FPGA for signal process. I want to config the ADC to output test pattern. But the ADC can't linked with the FPGA, is it possible just use Sysref signal to link the JESD?

   I have upload the waveform of sysref and clk, please help me check if the timing is correct, yellow curve is sysref, blue one is clk, the clk is 122MHz

   Thanks in advance.

Best wishes

  • Hi Chunsong,

    This device requires following JESD204B standard. This means that to begin the link bringup to the FPGA, first a CGS (code group synchronization) request must be made. This is initiated by assertion of the SYNC signal (active low). After CGS phase is completed, the device will enter ILAS (initial lane alignment sequence) phase of the bring up process, the FPGA will de-assert  the SYNC signal upon completion of ILAS, indicating to the ADC that the FPGA is ready to receive actual sample data instead of K28.5 characters.

    Please refer to this document for the following image: https://www.ti.com/lit/ml/slap160/slap160.pdf 

    Thanks, Chase

  • Hi Chase

        Thanks for  your reply.

        There is no SYNCb signal on ADC32J25, is that means SYNCb is just a internal signal? I just need to transmit the sysref signal from the FPGA.  

         From the datasheet, I see the the sync signal need a low-high transition to get the k28.5 code output. Is that means I need connect both SYNC and SYSREF on ADC side and FPGA side? Currently, I just connect the sysref pin.

    Best wishes

  • Hi Chunsong,

    The SYNCb signal is called SYNCP~ and SYNCM~ for this device. SYNCb is an active low syncronization signal used with JESD devices to initialize the link. Without this signal, you will have to use a serial SYNC request via registers (which is not a recommended approach during design as some devices do not support serial SYNC requests). In the case of this device, you can swap the SYNCb pulse using register 0x3A. This can be done by first setting SYNC REQ EN as 1 and then toggling the SYNC REQ field to 1 and back to 0 after the FPGA begins the CGS phase. In this case, only having SYSREF is okay.

    Regarding the SYSREF frequency, this should be SYSREF = Fs / (N * K). In your case, if Fs = 122MSPS, K is the JESD K value (found in register CTRL K and FRAMES PER MULTI FRAME), N can be any integer value and is flexible.

    Thanks, Chase

  • Hi Chase

       Per my understanding, SYNC and SYSREF are all input signal for ADC.

       What could I observed if I set SYNC REQ EN to 1? Can I measured the data waveform on the data trace?

       Another questions is if I set the PDN PIN DISABLE to 1(set regiser 0x15h to 1), I could see the clk waveform on the data trace, is there anything wrong of my setting?

    Best wishes

  • Hi Chunsong,

    If you set SYNC REQ EN to 1, this places the ADC into serial sync mode, ignoring any inputs to the physical SYNC pins. Nothing will happen until the SYNC REQ bit is toggled. Please find this resource useful: https://www.ti.com/video/series/jesd204b.html 

    If you set PDN PIN DISABLE field to 1 in register 0x15, you have to also set the GLOBAL PDN field in the same register to 1 to powerdown this device. The PDN PIN DISABLE field simply tells the ADC to ignore the input and to instead use the register setting for powerdown.

    Thanks, Chase

  • Hi Chase

        I have done some rework on my board by using SYNC~P/SYNC~M instead of SYSREF, but I still can't measure  any waveform on the data output trace. I suppose there should be K28.5 waveform on the trace. Is the ADC could work just have sync signal without sysref?

       And I found the timing in datasheet is different from the timing in the ppt. I have sent a low to high sync transition by FPGA like the figure145 in the datasheet. But I didn't see K28.5 on the data trace. Is that means the SYNC signal and SYSREF signal should be both connected to FPGA?

       How about FPGA send a high-low transition? Can I see the K28.5 on data trace in this case? 

       

    Best wishes

  • Hi Chunsong,

    The figure 145 is showing the latency between the previous SYNC~ transition and the ending of the CGS phase (also the beginning of the ILAS phase). SYSREF is required for deterministic latency which is what we recommend (JESD204B subclass 1). If device is configured, SYSREF is a valid frequency, and FPGA toggles the SYNC~ signal from high to low, the device should start transmitting K28.5 symbols. This will show up the FPGA ILA as a repeating value of 0xBC. Can you enable SYSREF and retry?

    Thanks, Chase

  • Hi Chase

       OK, I will change the SYSREF back and update the test result once it is done.

    Best wishes

  • Hi Chase

        Sorry for the late response, I have changed back to use SYSREF. But after the configuration, the ADC output is always high level.

        My config procedure is as below:

    • Write 0x3A==0x40
    • Write 0x3A==0xC0
    • Write 0x06== 0x02
    • Write 0x09== 0x02
    • Write 0x0A== 0x03
    • Write 0x0B== 0x30
    • Write 0x3A==0x40 
    • Measure the waveform on ADC data output path.

       Could you please kindly help to check is there anything wrong of my test setup? Do I need to set  SYNC REQ EN to 0?

    Best wishes

  • Hi Chunsong,

    Yes, we will review this and get back with you.

    Regards

  • Hi Chase

        Sorry I have another query that is it possible to use single end connection of SYNC and SYSREF? Because lack of GPIO resource of FPGA, I need to save some pins in next build.

        And I have put my ADC schematic here, could you please help to comment? SyncP and SyncM is not connected to FPGA, just leave a resistor outside.

        I need to use a external wire to connect it. And it seems there is still something wrong of the FPGA output. I have to use manual sync.

    Best wishes

    Chunsong

  • Hi Chusong,

    Since this is a separate question, can you please open another thread for us to address?

    Thank you, Amy