Hello
I am bringup a demodulator which need to use ADC to convert the data to FPGA for signal process. I want to config the ADC to output test pattern. But the ADC can't linked with the FPGA, is it possible just use Sysref signal to link the JESD?
I have upload the waveform of sysref and clk, please help me check if the timing is correct, yellow curve is sysref, blue one is clk, the clk is 122MHz
Thanks in advance.
Best wishes