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ADS131M04-Q1: Sigma-delta ADC selection questions - (clock rates, sample rate, input range)

Robert Murphy
Prodigy 30 points
Part Number: ADS131M04-Q1
Other Parts Discussed in Thread: ADS131M04

Looking for review of an ADC part selection - ADS131M04.   Our application has a fully differential OpAmp driving a 6" mico-coax cable.   The Diff Amp is powered with +/-2.5V and has a single ended input of 0 to 2.5V.  This should result in an AINxP signal of 0 to +1.25 and an AINxN signal of 0 to -1.25V.

Our questions,

1)  We are considering offsetting the Diff amp so the single ended range is -approximately -1 to +1 V to the Diff Amp input.  In this case the Diff output voltage to the ADC will be +/500mV on each input (AINxP ,AINxN ).  The question is does the AINxN input accept negative voltages from a differential amp?  Some of the ADC in the series do not.  It appears that it does, but a similar part (ADS121B04) states the min analog input as AGND - 0.1.  

2)  Does this type of ADC (sigma delta) require any local buffering to avoid kick-back or other signal data acquisition errors.

3) Can the part be clocked such that the output rate is ~10kHz?  For example, if the OSR is 256 the clock would be 5.12MHz.

3) Given that there are (4) ADCs that are simultaneous, it is assumed that the stated sample rates at the different clock rates and OSR values are for all 4 channels.  For example, Clock = 8.192MHz, OSR = 256, the sample rate for all 4 channels is 8Ksps.

Thank

Rob.

  • 0
    TI__Mastermind 18900 points

    Hi Rob

    Robert Murphy said:
    1)  We are considering offsetting the Diff amp so the single ended range is -approximately -1 to +1 V to the Diff Amp input.  In this case the Diff output voltage to the ADC will be +/500mV on each input (AINxP ,AINxN ).  The question is does the AINxN input accept negative voltages from a differential amp?  Some of the ADC in the series do not.  It appears that it does, but a similar part (ADS121B04) states the min analog input as AGND - 0.1.  

    Yes, see the recommended operating conditions section:

    Robert Murphy said:
    2)  Does this type of ADC (sigma delta) require any local buffering to avoid kick-back or other signal data acquisition errors.

    I think you're asking if we need a buffer on the input pins (AINx)? The answer is no because of the input PGA. Its very typical to connect the sensors directly to the inputs (with anti-aliasing filters of course). 

    That being said, I would recommend looking into the input impedance based on your gain and clock settings. 

    Robert Murphy said:
    3) Can the part be clocked such that the output rate is ~10kHz?  For example, if the OSR is 256 the clock would be 5.12MHz.

    Yes, the math works perfectly for that OSR and f_CLKIN value. Note bandwidth will be much lower than that

    10k*0.25 = 2.5kHz -3dB bandwidth.

    Robert Murphy said:
    3) Given that there are (4) ADCs that are simultaneous, it is assumed that the stated sample rates at the different clock rates and OSR values are for all 4 channels.  For example, Clock = 8.192MHz, OSR = 256, the sample rate for all 4 channels is 8Ksps.

    Yes, the OSR value is applied to all 4 channels. You cannot configure them separately. 

    Best,

    -Cole