Hi
I have opened a new thread for the schematic query.
e2e.ti.com/.../adc32j25-adc-jesd-can-t-link-with-the-receiver-fpga
In the datasheet of ADC32J25, Sync and Sysref need to use a differential circuit, is it possible to use a single end trace instead of differential trace?
And could you please help to comment the schematic? Because on my current design, the adc can't linked with the FPGA.
Best wishes
Zhigang