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ADC32J25: Does Sync and Sysref could use a single end trace not the differential trace

Part Number: ADC32J25

Hi

   I have opened a new thread for the schematic query.

   e2e.ti.com/.../adc32j25-adc-jesd-can-t-link-with-the-receiver-fpga

   In the datasheet of ADC32J25, Sync and Sysref need to use a differential circuit, is it possible to use a single end trace instead of differential trace?

   And could you please help to comment the schematic? Because on my current design, the adc can't linked with the FPGA.

Best wishes

Zhigang