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ADC12DJ4000RFEVM: Interfacing with Xilinx VCU118 Eval Board

LALIT VERMA
Expert 1645 points
Part Number: ADC12DJ4000RFEVM

Hi,

I want to use Xilinx VCU118 board for testing JESD204C linkup with ADC12DJ400RFEVM.

I have checked the schematic of ADC12DJ4000RFEVM, SPI signals are referenced to 1.9v but GPIO mapped to FMC+ connector on VCU118 are referenced to 1.8v. 

Now, that should be ok for CS,SCLK and MOSI but MISO, which is input to FPGA, will be an issue because with MISO, voltage level on FPGA pin will be 1.9v but the VCC of the FPGA bank is 1.8v.

Have TI already tested ADC12DJ4000/5200RFEVM with VCU118 or any other Xilinx Eval board?

Thanks,

Lalit

  • 0
    TI__Mastermind 21125 points

    Hi Lalit,

    Yes, we have tested this EVM family with a variety of xilinx development platforms, however for these test the SPI will have been sent over the ADC EVM's USB port, not over the FMC interface from the FPGA. I would suggest asking xilinx about the results of applying a 1.9V SPI signal to their 1.8V FPGA bank. Chances are it is fine, but I suggest you verify with them first before trying anything. We cannot confirm this info for you.

    Regards  

  • 0 in reply to Chase W
    Expert 1645 points

    Hi Chase,

    Thanks for the reply.

    I have one more question.

    I can see that on ADC12DJ4000 eval board some JESD serdes lanes polarity are inverted. Is there any register in ADC12DJ4000 using which we can invert the P and N polarity inside the ADC?

    And if there is not any such register, then how TI have verified that all 16 JESD lanes are working fine with VCU118 or any other xilinx board?

    Thanks,

    Lalit

  • +1 in reply to LALIT VERMA
    TI__Mastermind 21125 points

    Hi Lalit,

    This device itself does not have any lane polarity option. The polarity inversion/correction is performed on the FPGA in firmware for devices like this. Our newer devices have the option for lane mapping and lane polarity corrections and we now lean towards performing the corrections on the device rather than FPGA wherever possible.

    Regards, Chase