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ADS8688A: SPI SDO output setup and hold times

Jason Chang
Prodigy 40 points
Part Number: ADS8688A

Hi,

I wanted to get some clarification on the timing requirements for the SPI interface. On the datasheet, it talks about required setup and hold times for SDO (SPI output). What is it specifying? I don't believe outputs usually will have setup and hold requirements. 

Thanks

  • 0
    TI__Guru 63196 points

    Hi Jason,

    Thank you for your post.

    In this case, the setup time (tSU_DOCK) is the minimum about of time the controller must wait after the SCLK rising edge before latching the data on the falling edge. In other words - 25 ns is the maximum time the SDO pin is expected to take for a change in output to settle so that it can be read.

    The hold time (tHT_CKDO) is how long you must wait after the SCLK falling edge before issuing another rising edge, which would cause SDO to change to the next bit. This ensures that SDO remains stable for at least 10 ns after the capture edge and is read correctly.

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    Prodigy 40 points

    Hi Ryan,

    Can you clarify on tSU_DOCK being with respect to the SCLK rising edge? When I zoom into the timing diagram, I see that tSU_DOCK is drawn from the edge of the valid data to the next falling edge of the clock. 

    Thanks,

    Jason

  • 0 in reply to Jason Chang
    TI__Guru 63196 points

    Hi Jason,

    I see your point. I believe this is just misdrawn a bit. The rising edge of clock produces the change in SDO; therefore, it should align with left side of the "X" before the data begins to transition.

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    Prodigy 40 points

    Hi Ryan,

    Looking through the datasheet, all of the documentation mentions SDO being updated on the falling edge of the clock. Does this mean that the "hold time" for SDO will be the delay for SDO after a falling edge of SCLK?

    Thanks,

    Jason

  • 0 in reply to Jason Chang
    TI__Guru 63196 points

    Hi Jason,

    Actually - you are correct. Data is only launched on the SCLK falling edge. The capture edge is technically up to your controller's timing capabilities, but we recommend capturing on the opposite edge.

    With that in mind, the way to interpret the specs are as follows:

    1. tHT_CKDO: this is drawn correctly in Figure 1. The previous data bit will remain on SDO for at least 10 ns after the SCLK falling edge. This spec becomes important only if you are trying to capture data on the same edge that's used to transition the next SDO bit. If your system cannot reliably maintain timing closure within this spec, it's best to wait until the opposite clock edge to read the data.

    2. tSU_DOCK: this is still not drawn properly. The setup time should begin at the clock falling edge and measure ahead in time to when the data transition is settled. This tells the controller how long to wait for the new data in the event it is reading on the opposite clock edge (as recommended above). I have redrawn the tSU_DOCK below:

    Regards,

    Ryan