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ADS131B04-Q1EVM: Communication with ADS131B04Q1-EVM works when PHI is attached

Part Number: ADS131B04-Q1EVM
Other Parts Discussed in Thread: ADS131B04-Q1, LP5907


I have noticed that comms with the ADS131B04Q1-EVM works more reliably (specifically the reset command) when the PHI is attached, even when the PHI is not powered!

I am powering the board using TP1 and TP2 for AVDD and DVDD respectively from an MCU development board. I have removed R45. All of the header pins on J6 are in use apart from DIGITAL.CLK as I am using the on board 8.192 MHz oscillator.

Is there any obvious reason for this? Can you provide a schematic for the PHI board? I just want to make sure that the FPGA isn't providing some extra signals that I am missing as I intend to use the ADS131B04 ADC on our specific design and so need to have confidence in the firmware.



  • Hi Tim Guite,

    If you want to use an external controller with the ADS131B04-Q1 EVM, disconnect the PHI board. Even though you have disconnected the power from the EVM_DVDD net, it is possible the control signals are back-powering some of the PHI board since they are still connected.

    There is also no obvious reason why the RESET command would work better with the PHI attached. This seems like it's actually obscuring some other issue

    Do you have a strong ground connection between your controller card and the EVM?

    Also, what happens to the RESET command? Is it issued correctly from your controller, but the device does not RESET? If might be helpful to see the digital communication so we can diagnose any potential problems. If you have a Saleae logic analyzer you can send us the .sal file for review (please include in a zipped folder, don't directly upload the .sal file to e2e)


  • Hi Bryan, thanks for clarifying! The ground connection should be relatively good because that is connected via the jumper pins. The power connections - AVDD and DVDD - are a bit more tenuous as they are just forced through the test points and not really secured or joined properly. I might solder them on tomorrow to see if this helps. Am I right in thinking that 3.3V through TP1 and TP2 should be sufficient to power the ADC? I.e there is no need for the 5V connection which is provided by the PHI?

    When the IC starts up, I can see the 0xFF44 message on first communication, indicating a recent reset. It also seems to trigger reset when I pulse the SYNC/RESET line low but then sometimes is ignoring commands such as resets, read register and write register, just returning a status of 0x050F to all of these. I have found it to be more reliable when the PHI board is attached but not powered (hence my question).

    As you state, there is probably a hardware issue somewhere in my setup. When I have tried adding more jumper connections via breadboard to include a logic analyzer the comms becomes very patchy. Again, probably a hardware issue on my end if I'm not missing anything obvious.

  • Hi Tim Guite,

    Connecting a logic analyzer should not impact the communication under normal circumstances, so this certainly sounds like a hardware issue. If you want to send a picture of your setup that might help rule some things out


  • Hi Bryan, that makes sense.

    Can you please confirm that 3.3V through TP1 and TP2 should be sufficient to power the ADC? I.e there is no need for the 5V connection which is provided by the PHI?

  • Hi Tim Guite,

    Yes you can power both AVDD and DVDD on the ADS131B04-Q1 using 3.3V. In fact this is the required configuration, as per the recommended operating conditions table shown below from the ADC datasheet. The 5V from the PHI is stepped down to 3.3V through the LP5907 LDO