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ADS131M03-Q1: SPI Communication

Chris Willis
Intellectual 290 points
Part Number: ADS131M03-Q1

Hello,

The datasheet states “Connect either SYNC/RESET or DRDY to the MCU to ensure the MCU stays synchronized to ADC conversions.”

Figure 9-2 shows them connected to GPIO on the MCU.

But also says you can use the CLKIN periods to determine sample period.

Does anyone understand why one or both of these pins would be required to be connected to the SPI master / microcontroller / MCU?

Should a reset be issued before every data request or should the data request be initiated upon every DRDY transition or is it something else?

  • +1
    TI__Mastermind 22805 points

    Hello Chris,

    I am sorry, if we confused you with the descriptions in the ADS131M03-Q1 datasheet.

    There are multiple ways to determine if new data are available with this device. Depending on your preferred method, you need to make according pin connections then.

    • The most common method is to watch for a falling edge on the DRDYn pin.
      In this case you would connect the DRDYn pin to a falling edge interrupt triggering GPIO on the host.
      You could tie the SYNC/RESET pin high in that case.
    • You can also poll the DRDYx bits in the STATUS register to determine if new conversion results are available.
      You could tie the SYNC/RESET pin high in that case and leave the DRDYn pin floating.
    • In case the host controller provides the clock to the ADS131M03-Q1 on the CLKIN pin, then you could simple count clock cycles to determine when new conversions are available. The ADCs take a deterministic time based on clock cycles for each conversion.
      You could tie the SYNC/RESET pin high in that case and leave the DRDYn pin floating.
    • The SYNC/RESET pin option would usually be used when you try to synchronize multiple ADS131M0x-Q1, so that they all convert simultaneously.

    You should definitely not issue a reset before every data request.

    Regards,
    Joachim Wuerker