I am using Intel FPGA to receive data from AFE through the Jesd204b IP core. The AFE chip documentation tells me that each chip has two ADC die, and each die has 8 channels. I configured two dies in 80X mode with a sampling clock of 100MHz. According to the manual, I set the L, M, and F values for each die as 2, 8, 8. Since one AFE has two ADC die, based on my understanding, I configured the FPGA's IP core with L, M, and F values of 4, 16, 8, and the rate of each lane is 8G.
However, when I enable the demodulator function, the rate sent to the Jesd module decreases. In this case, do I need to reconfigure the values of M and F? If I don't reconfigure, the lane rate and the actual rate sent to the Jesd module will not match. For example, the data rate sent to jesd module will be only half of the lane rate. Will this cause any problem?
