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AFE58JD48: 1

alen
Prodigy 80 points
Part Number: AFE58JD48
Other Parts Discussed in Thread: LMK00308, LMK04832

I use an FPGA to synchronously receive data from 8 AFEs through the JESD204B interface subclass 1, how should I connect the clock and sysref signal to the AFEs and FPGA? I found that the LMK0482X chip only supports a maximum of 7 pairs of device clocks and SYSREF outputs. I'm not sure if I need to connect 8 pairs of device clocks and SYSREF to the AFEs, and additionally connect 1 pair of device clock and SYSREF to the FPGA. If so, the output of one LMK0482X chip would not be enough. All my 8 AFEs are operating in the same mode.

  • 0
    TI__Expert 6790 points

    Hi Alen,

    Thanks for reaching out.

    I got your question, kindly allow me to think of a possible solution to this.

    I will get back to you by tomorrow or earlier.

    Thanks & regards,

    Abhishek

  • 0 in reply to Abhishek Vishwa1
    Prodigy 80 points

    Thanks a lot! This is a solution I came up with based on my own understanding. I'm not sure if it's feasible or not.

  • +1 in reply to alen
    TI__Expert 6790 points

    Hi Alen,

    That is correct. 

    We will definitely have to use multiple devices. 

    The block diagram you have shown is very similar to the required one however we need to ensure the synchronization of between the two LMKs as well.

    I am discussing the possibilities of doing that with the clocking team. I will get back to you by evening.

    Thanks & regards,

    Abhishek

  • 0 in reply to Abhishek Vishwa1
    TI__Expert 6790 points

    Hi Alen,

    Thank you for your patience.

    After some considerations of power and optimization. I think using 2 LMK0482x is not great solution. It would be power hungry and there would be issues with correct synchronization across multiple devices/FPGA.

    I think you should use a combination of LMK04832 clock fan out buffer such as LMK00308 to do the clocking. 

    Since the device is NDA restricted. I am sharing a block diagram of the clocking scheme in one of our previous projects of 128 ch JD48 over email. 

    Thanks & regards,

    Abhishek