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DAC37J82: Configuration inquiry

JH Shin
Guru 11110 points
Part Number: DAC37J82
Other Parts Discussed in Thread: DAC37J84, LMK04806,

Hello,

My customer wants to use the DAC37J84 under the following conditions.

  - DACCLK P/N (Input CLK) = 1258.2912Mhz (From LMK04806)
  - DACCLK (PLL out) = 943.7184Mhz (DAC PLL used, PLL Lock ok)
  - pll_n=4, pll_p=5, pll_m=3, H-Band(pll_vcosel=0), pll_vco=21
   - DAC Fs = 943.7184Mhz

   - Line Rate = 9437.184Mhz
   - JESD Core clock = 235.9296Mhz (LineRate/40)
   - FPGA REF CLK = 314.5728Mhz
   - Full-Rate, Mpy=10, Serdes Refclk = 235.9296Mhz (div_by_4)
   - SYSREF = 3.6864Mhz (9437.184 / (80*32) = DataRate/(N x K))

   - LMFS = 8212 /  K=32, F=1

Q1) please review whether the following Register values set by the customer are correct for the configuration.

821_CHA_CHD.zip

Q2) When the DAC37J84 operates with the above settings, the following error occurs. Please advise on the cause of this issue and how to solve it.

  - DAC Sync stays low

  - Config100-107 = 0x0008 Lane FIFO errors: bit3 = write_error : Asserted if write request and FIFO is full

Q3) If they set jesdclk_div Setting (Config37) = 0xC000, DAC Sync turns to high, and Lane Alarm (config100~107) is also 0x0000.

        If Jesdclk_div is set to 2, 4, 8, or 16, sync is low and Lane Alarm also occurs. Is there a rule to set Jesdclk_div?

Thank you.

JH

  • +1
    TI__Mastermind 23760 points

    Hi JH,

    Please ensure the correct initialization startup sequence is being followed for this device. The FIFO error indicates the serdes FIFO is full while it is still being written to. This usually happens when the startup sequence is incorrect. All question you have asked are related to this so I will not be answering them individually.

    I'm confused which device is being used here. The post title says DAC37J82, but in the post it is DAC37J84. This is confusing me because only DAC37J82 can achieve LMFS of 8212. And when DAC37J82 is configured for Fs = 943.718M at 1x interpolation in LMFS=8212 mode, the serdes is 4718.59 MHz. The DAC37J84 with this sample rate achieves this serdes rate but the LMFS is instead 8411 as there are now 4 converters. Please get clarification from your customer for further assistance.

    After the configuration above is run, try writing the following to re-initialize the JESD link.

    0x4A  0xFF3E (places jesd_reset_n low)
    0x4A  0xFF3F (lifts the jesd_reset_n back high while leaving init_state low)
    0x4A  0xFF21 (releases the JESD block in the DAC out of init_state mode)

    Regards, Chase