ADS127L01EVM: SCLK settings

Hello Ernest,

Section 8.5.2.2.2 is applicable to Frame-sync communications, not SPI.  The SCLK relationship to CLK in the case of Frame-sync is a requirement for proper communications, and if this relationship is not met, then communications will not work correctly. 

When using SPI, this relationship is not a requirement for proper communication, but you will see an improvement in noise if you keep this recommended ratio.  You should not see an increase in total noise with little or no difference in Tables 1 and 2, but you will see an increase in noise spurs if running an FFT (the SFDR will be reduced).

1. Based on the section 8.5.2.2.2 (in data sheet), the setting of SCLK (the clock for SPI) should be any of-two ration of CLK cycles. So, is this means that for the CLK = 16MHz, the SCLK should be 16M Hz, 8M Hz, 4Mhz, or etc? 

Yes, this is correct, but only a requirement for frame-sync.  For SPI, this relationship is recommended for lowest noise.

2. Would it be any data loss issue if 12Mhz SCLK is used for CLK = 16MHz? 

If using Frame-sync, then yes, there will be a loss of data.  If using SPI, communications will be reliable and there will be no data loss.

Regards,
Keith Nicholas
Precision ADC Applications