Other Parts Discussed in Thread: LMK04828, AFE7950


Found in ZCU102_AFE79xx_64b66b_12Gbps reference designBased on TI_IP_12Gbps_8Lane_ConfigLmk.py
I am trying to change the settings of LMK04828, FPGA, and ADC to AFE7950_EVM.
What I want to doPLL the 80MHz VCXO from the 10MHz reference and create 1280MHz from 80MHz with the VCO
inside the PLL.Divide it to create 128MHz and 256MHz as shown in the LMK04828 connection change list.
I want to output.
There is no place in any of the scripts where DCLK*/SDCLK* is specifically changed.Do I need to modify the library?
Please teach me.