Questions for TI ADC.
- When utilizing the ADC serial interface, what is the maximum period that reset can be asserted to logic ‘1’ before the ADC reverts to parallel configuration mode ?
- When utilizing the serial interface configuration mode, with respect to config word 00, is there a wait time required if bit[4] is asserted (reset) before configuring the next word ?
Thank you.
Zlatko Pikal
Galvanic Applied Sciences Inc.
Email: zpykal@galvanic.com


