Hi,
I am using ADS7057 in one of my design. While using the ADC i am getting erroneous signal levels in the SDO pin of the ADC. I am attaching herewith a photo of the CRO waveform. In this the yellow signal is SDO, blue is the SCLK and the red is CS signal. The SPI clock is supplied by a custom SPI core and is given as two sets of 9 clock cycles while keeping the CS signal low
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As you can see the SDO line is not stable at logic 1 or 0. I am using 2.5V Vref and 3.3V as DVDD. The SPI clock is 20MHz
Regards,
Varun M J
