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Original question:

ADS131M03: About clock input spec

ADS131M03: fCLKIN vs Noise, and power mode vs Noise

Luke Sakamoto
Intellectual 1605 points
Part Number: ADS131M03

Hi team!

My customer is interested in this IC and has further questions about the noise spec.

Below table is from page15. It is when the master clock is set at 8.192 MHz.

I understand that the modulation clock and the filter clock (mod clock/OSR) are critical parameter for the above noise values.

Q1. My customer needs the noise values & DR values when the2MHz, 1MHz, 300kHz. Do we have some values here? How one can calculate these values?

Q2. Can you tell us the mechanism and the relation ship of Noise and DR vs High-resolution mode/Low-power mode/VLP?

Thanks,

Luke

  • 0
    TI__Mastermind 39225 points

    Hi Luke,

    I have seen you are asking the similar questions about the same ADC, you can find the answers in your previous post below:

    ADS131M03: About clock input spec

    Can you please put the customer's name into the "Note" field above? thanks.

    Regards,

    Dale

  • 0 in reply to Dale Li
    TI__Intellectual 1605 points

    Hi Dale,

    Thanks for your continuous support.

    The previous question has been "resolved"; hence, i am making another thread.

    Futhermore, the questions I asked in this thread is not covered in the previous thread.

    Please answer them separetely.

    Thanks,

    Luke

  • 0 in reply to Luke Sakamoto
    TI__Mastermind 39225 points

    Hi Luke,

    Q1: all data have been included in the datasheet. As I said in your previous post, the noise is mainly related to the OSR, the noise is same if the OSR is same under the different master clocks.

    Q2: as I said, the noise is determined by the OSR, not the data rate that depends on your OSR configuration and the master clock the customer actually uses.

    Regards,

    Dale

  • 0 in reply to Dale Li
    TI__Intellectual 1605 points

    Hi Dale,

    Thanks for your reply.

    Your answer makes sense.

    An additional question:

    The only characteristic difference for High-resolution mode, Low-power mode, and Very-low-power mode I was able to find in the datasheet was the External clock frequency.

    Does this mean that the differences of these modes are there to unlock the upper frequency max values? (hence, higher OSR can be achieved?)

    Are there other key features am I missing in terms of the performance differences v.s. modes?

    Thanks,

    Luke

  • 0 in reply to Luke Sakamoto
    TI__Mastermind 39225 points

    Hi Luke,

    The OSR from 64 to 16384 is same for these three modes. The higher data rate can be achieved with the higher master clock frequency under the same OSR configuration. Also, the modulator clock frequency has to be reduced to save power, so the master clock frequency in LP and VLP mode is limited.

     All information are shown in the data sheet. Except the performance, these modes have different power consumption.

    Regards,

    Dale