Other Parts Discussed in Thread: ADS7038, ADS7038Q1EVM-PDK
From the documentation www.ti.com/.../ads7038-q1.pd
8.3.4 ADC Offset Calibration
The variation in ADC offset error resulting from changes in temperature or AVDD can be calibrated by setting the
CAL bit in the GENERAL_CFG register. The CAL bit is reset to 0 after calibration. The host can poll the CAL bit
to check the ADC offset calibration completion status.
Multiplexer sequencing must be stopped (SEQ_START = 0b) before initiating offset calibration.
The ADC calibration bit never auto-resets for our ADS7038Q1EVM-PDK setup. Steps:
- Set GENERAL_CFG:RST
- Check SYSTEM_STATUS:SEQ_STATUS (0b), SEQUENCE_CFG:SEQ_START (0b) and GENERAL_CFG:CAL bits (0b)
- Set the CAL bit
- Check CAL bit (1b). After 30 minutes, it is still set
