• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 244 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1282-SP: Clock Jitter requirement

Steve Widener
Genius 10185 points
Part Number: ADS1282-SP

The datasheet mentions that a low-jitter clock is essential for optimum performance, but doesn’t recommend any typical values for jitter. What jitter  is recommended for a DC measurement (essentially a RTD temperature measurement)? If we are unable to provide a clock with low jitter, what impact does this have on the ADC? Will it affect the ENOB?

  • +1
    TI__Mastermind 40990 points

    Hi Steve,

    For a DC measurement, the jitter of the clock does not impact noise at all!  However, there is always some upper frequency of interest that is non-zero.

    This TI Precision Labs presentation provides some details on the calculation of jitter based on the input signal frequency, OSR setting and the required SNR, or Dynamic Range of the system.

    https://www.ti.com/content/dam/videos/external-videos/8/3816841626001/6242062186001.mp4/subassets/adcs-sar-delta-sigma-noise-and-drive-considerations-presentation.pdf

    Since you are measuring an RTD at DC, I will assume you are using the lowest data rate setting to get the lowest possible noise.  In this case, using the 250sps data rate (OSR=4096), the best possible SNR due to thermal noise will be at a PGA gain of 1, SNR=130dB. 

    Let's be generous and assume that we are concerned with an input signal frequency up to 100Hz.  Also, since we do not want to degrade the thermal noise by jitter, we will target a jitter limited SNR of 20dB higher, or 150dB.  Plugging these numbers into the below jitter equation and solving for t-jitter results in a maximum jitter of t-jitter=3.2ns-rms.  Just about any crystal oscillator will easily meet this specification; most are better than 100ps-rms. 

    At DC, the clock jitter will not impact ENOB.  Most of TI's delta-sigma ADC's that are focused on temperature measurements use an internal RC oscillator, which has more than 1ns of jitter.

    The statement in the datasheet is really concerned with higher bandwidth signals greater than 1kHz in bandwidth.  In these cases, limiting jitter to 100ps or lower is usually recommended.

    Regards,
    Keith Nicholas
    Precision ADC Applications