Hi Team,
Pin configuration: PD is configured for default pulldown, PLL_EN, PLLREF_SE is pulled high by default, and external clock is selected as 50M signal input. The register configuration address and register values are configured in the following picture order, in fact the ADC PLLREF_CLK output normally outputs a 50 MHz signal, but the TRIGOUT± set is not.
In the original design, setting is seen as FPGA GTH recovered clock, but now shows no output.
When TLR_out enters FPGA and then MREFCLK, the MREFCLK clock frequency always has been unstable. The FPGA uses ultersclae architecture zukc060.
The clock connections are as follows:
VCO_CAL_status is read during the configuration process, VCO_CAL_status[7:1] is a reserved bit and 0 bit is the VCO_CAL_done status bit through the registers.
However, during an actual read, a 0x30 is read after multiple 0x20 reads. But the acquisition trigger clock is still unstable.
Could you help check this case? Thanks.
Best Regards,
Cherry
