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ADC09QJ1300-Q1: TRIGOUT output is unhealthy

dami yang
Prodigy 10 points
Part Number: ADC09QJ1300-Q1
Other Parts Discussed in Thread: LMK00304

hi TI engineer：

I am having some problems with the ADC adc09QJ1300-Q1.My electrical connection is shown below

The corresponding value of the sequential address of my register configuration is shown in the figure below

     

and use tirgout as the recovery clock for FPGA GTH.FPGA type is ulterslcae xcku060,and clk in fpga is shown in the figure below

but the trigout clock output is unstable, but pllref is stable at 50Mhz。and The VCO_CAL_STATUE is read during configuration, and it is known from the registers that VCO_CAL_STATUE[7:1] is the reserved bit and bit 0 is the VCO_CAL_DONE status bit。However, in the actual reading process, multiple 0x20 are read and then one 0x30 is read. However, the acquisition trigout clock is still unstable. What is the question you want to ask? 

  • 0
    TI__Expert 4210 points

    Hello Dami,

    Can you provide a picture of the clocks output from the LMK00304 using an oscilloscope please.

    Thanks,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 10 points

    hi Eric,

    This issue is caused by the cpll configuration feedback clock being less than 50Mhz and not locking. But now the CAL_STATUS registers are read, and the read value is 0x01, which means that the cpll is locked, but the serdes pll is not. Then the test data link in Test mode also has no data.This is a serdes pll configuration where is the configuration problem?

    Thanks!

  • 0 in reply to dami yang
    TI__Expert 4210 points

    Hello Dami,

    The issue of the serdes pll locking means that your FPGA is not getting the correct clock frequency. Could report the value of the register JESD_STATUS (0x208) and could you let me know your desired sampling rate.

    Thanks,

    Eric Kleckner

  • 0 in reply to Eric Kleckner
    Prodigy 10 points

    hi Eric,I report register value as follows:

    VCO_CAL_STATUE（0x005e）= 0x03；
    JESD_STATUS（0x0208）= 0x01；
    CAL_STATUS (0x006a) = 0x0c;
    and my regsiter set value as follows:
    adc_reg_addr[0]  = 16'h0000;    adc_reg_da[0]  = 8'hB0;  // CONFIG_A        // RESET
adc_reg_addr[1]  = 16'h8270;    adc_reg_da[1]  = 8'h00;  // INIT_STATUS --READ  // INIT_STATUS --READ
adc_reg_addr[2]  = 16'h005C;    adc_reg_da[2]  = 8'h01;  // CPLL_RESET      // set CPLL_RESET == 1,before programe cpll reg
adc_reg_addr[3]  = 16'h003F;    adc_reg_da[3]  = 8'h4A;  // CPLL_VCOTRL1    // use c-pll default value vco_bias = 0x4a
adc_reg_addr[4]  = 16'h0058;    adc_reg_da[4]  = 8'h01;  // CPLL_OVR        // C-Pll config use SPI ; output cpll ref_clk divided by 1 on ORD
adc_reg_addr[5]  = 16'h003D;    adc_reg_da[5]  = 8'h04;  // CPLL_FBDIV1     // P = 2;
adc_reg_addr[6]  = 16'h003D;    adc_reg_da[6]  = 8'h05;  // CPLL_FBDIV1     // V = 4; fs = 8/v/p = 1Gbps
adc_reg_addr[7]  = 16'h003E;    adc_reg_da[7]  = 8'h14;  // CPLL_FBDIV2     // N = 20;fref = fs/N = 50M  
adc_reg_addr[8]  = 16'h005D;    adc_reg_da[8]  = 8'h41;  // VCO_CAL_CTRL    // VCO_CAL_CTRL,VCO_CAL_EN = 1,  
adc_reg_addr[9]  = 16'h005C;    adc_reg_da[9]  = 8'h00;  // CPLL_RESET      // clear CPLL_RESET == 0,finish cpll config;
adc_reg_addr[10] = 16'h0057;    adc_reg_da[10] = 8'h01;  // TRIGOUT_CTRL    // set RX_DIV = 32; TrigOut = 6.25/32 = 195.3125Mhz
adc_reg_addr[11] = 16'h0057;    adc_reg_da[11] = 8'h81;  // TRIGOUT_CTRL    // set TRIGOUT output enable;
adc_reg_addr[12] = 16'h002B;    adc_reg_da[12] = 8'h05;  // CLK_CTRL2       // CLK_CTRL2
adc_reg_addr[13] = 16'h0200;    adc_reg_da[13] = 8'h00;  // JESD_EN         // set JESD_EN = 0;
adc_reg_addr[14] = 16'h0061;    adc_reg_da[14] = 8'h00;  // CAL_EN          // set CAL_EN = 0 , hold calibration in reset to program new calibration settings
adc_reg_addr[15] = 16'h0201;    adc_reg_da[15] = 8'h0a;  // JMODE           // JMODE 10
adc_reg_addr[16] = 16'h0202;    adc_reg_da[16] = 8'h1F;  // KM1             // KM1 = 31; KM1 = k - 1; K = 32;
adc_reg_addr[17] = 16'h0207;    adc_reg_da[17] = 8'h02;  // FCHAR-K28.5     // K28.5
adc_reg_addr[18] = 16'h0205;    adc_reg_da[18] = 8'd07;  // TEST            // K28.5 Test mode enable
adc_reg_addr[19] = 16'h0204;    adc_reg_da[19] = 8'h03;  // JCTRL           // JCTRL enable scrambler enabled;SYNC_SEL
adc_reg_addr[20] = 16'h0213;    adc_reg_da[20] = 8'h0F;  // OVER_CFG        // enable over range;over-range output 4*2^7 sample cycles;
adc_reg_addr[21] = 16'h805e;    adc_reg_da[21] = 8'h00;  // VCO_CAL_STATUE --read   // ------- read vco_cal_done
adc_reg_addr[22] = 16'h8208;    adc_reg_da[22] = 8'h00;  // JESD_STATUS --read      // ------- read cpll_locked
adc_reg_addr[23] = 16'h0061;    adc_reg_da[23] = 8'h01;  // CAL_EN          // CAL_EN
adc_reg_addr[24] = 16'h0200;    adc_reg_da[24] = 8'h01;  // JESD_EN         // JESD_EN
adc_reg_addr[25] = 16'h006C;    adc_reg_da[25] = 8'h00;  // CAL_SOFT_TRIG   // CAL_SOFT_TRIG
adc_reg_addr[26] = 16'h006C;    adc_reg_da[26] = 8'h01;  // CAL_SOFT_TRIG   // CAL_SOFT_TRIG
adc_reg_addr[27] = 16'h006A;    adc_reg_da[27] = 8'h00;  // CAL_STATUS      // ------- read cal_status[0] = 1;
    it's set clk is jmode = 10;mean fs = 1Gbps,cpll fref = 50Mhz, line rate is 6.25G. 8 lines and 8b10b code ;
    and Trig_out is set ftrig = 6.25G/32 = 195.3125Mhz; sysref is 390.625khz; so how to set the correct clock frequency ?
    Thanks!
  • 0 in reply to dami yang
    TI__Expert 4210 points

    Hello,

    Sorry for the delayed response.

    The correct clock frequency for the fpga reference will be dependent on the way you have configured your receiver on your FPGA. Can you let me know what that frequency is.

    Thanks Eric