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ADS9817: Specification of AC Coupled Differential Sampling Clock

toshi-e2e
Genius 4760 points
Part Number: ADS9817

Hi all,

What is the minimum amplitude width specification, like the minimum VID for the SMPL_CLKP and SMPL_CLKM pins during differential input?

The data sheet also states the following:

"Clock amplitude impacts the ADC aperture jitter and consequently the SNR. For maximum SNR performance, provide a large clock signal with fast slew rates."

Does this mean that a signal input such as LVDS is inappropriate?

Thanks in advance.
Regards,
Toshi

  • +1
    TI__Guru 60546 points

    Hello Toshi-san,

    Thank you for your post.

    Both CMOS and LVDS sampling clock are perfectly suitable for ADS9817 and can achieve datasheet specifications. I think the more important spec here is the fast slew rate and low jitter of the sampling clock, which will ensure SNR is maintained for higher input frequency signals. 

    Regards,

    Ryan