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DAC5687: Timing spec questions

Kazuhiko Hirano
Genius 12423 points
Part Number: DAC5687

Hello,

My customer has some questions about timings as follows.

Q1:
In datasheet figure 50, what ns is the minimum ts(TXENABLE)?

Q2:
Any minimum th(TXENABLE) spec?

Q3:
Datasheet specifies minimum ts(SDENB), but how about minimum th(SDENB)?
Any minimum spec for th(SDENB)?

Best regards,

K.Hirano

  • 0
    TI__Intellectual 1960 points

    Hello Hirano-San, 

    Any specs that are not in the datasheet are not going to be available at this time unfortunately. Does the customer need deterministic timing on the TX-enable signal?

    For SDEN typically it is held high as long as the transaction is not taking place. There are typically no short pulses of SDEN, therefore hold time is not really important.
    What I typically do when writing a SPI pattern is wait until the last clock strobe is complete and wait an additional half clock cycle to pull SDEN high again. You'll always meet timing that way. Is the customer using an FPGA for SPI?

    Regards, 

    Matt