It seems like the datasheet only calls out specific spec's for when using LVDS for the CLK+/- reference clock input, and none specific to LVPECL. It says whenever DEVCLK_LVPECL_EN is set to (1) the internal termination becomes a 50-Ohm resistor to ground. Typically LVPECL drivers are terminated to ground, and the receiver is set to some common mode voltage. Or, the receiver uses a termination network of 50 Ohm in series with RTT to ground. Do you have any suggestions on termination techniques for this part using LVPECL with the receiver 50 ohm terminated, Preferably AC coupled.
Also, the datasheet says the internal termination ZT is set to 100 Ohm when DEVCLK_LVPECL_EN = 0 but also says ZT is set to 50 Ohm when DEVCLK_LVPECL_EN = 1.
But, further down in Table 8-60 it says ZT becomes a 50 Ohm term to ground when DEVCLK_LVPECL_EN = 1. I assume the documentation in table 8-60 is correct, and the ZT values in the Recommended Operating Conditions are a typo, unless I'm missing something.
