Part Number: AFE881H1EVM
Hi Joseph,
I've written CONFIG register data, on SDI = 0x02,0x00,0x75,0x9A
To read CONFIG register data, written SDI = 0x82,0x00,0x00,0xDD
read data on SDO was 0x04,0x00,0x01,0xBA but not get written data into register.
I captured data using logic analyzer for your review
Could you support us here on what is causing the issue to get actual data written?
Asha G
Asha,
In your logic analyzer post, I've circled three things that I think are wrong in the communication.
First, for every communication with the device, the /CS should return high. Each word sent to the device is separated by the /CS transitions.
Second and third, the data being sent to the has the wrong CRC value. For the first word, 0x10 0x00 0x00, the CRC should be 0xA2 not 0xA3. For the second word, 0x04 0x00 0x01, the CRC value should be 0xAC not 0xBA.
I did check this against the device responses. The CRC values coming out of the device are correct. I would note that some of your code should be working or the device wouldn't be responding at all.
Joseph Wu
Hi Joseph,
here is my sequence.
1. power on reset
2. SDI = 02 00 08 75 32
3. SDI = 00 00 00 00
4. SDI = 82 00 00 DD
Recv'd data on SDO
10 00 00 A2
10 00 00 A1
10 10 EB 7C
unable to read register data 08 75.
Asha G
Asha,
I've sent you a friend request in E2E and you can use the messaging tool that at the upper right corner of the E2E page. You can use that to attach files.
At this point, I think you are close to communication, but you have a timing issue with either the logic analyzer or with the SPI. To solve this problem, I'd still like to see the Saleae file. For example in the last logic analyzer plot, you can see that the write and the read are very similar.
Most of this error is that the DOUT is shifted over by one clock. My guess is that that the SDO is being misread by the Saleae.
Regardless, you can try to send the file through the messaging tool.
Joseph Wu
Asha,
I looked at your file and was able to open it. I think the problem right now is the way you have SDO setup with respect to SCLK. You can see this in the logic analyzer plot:
Here the SDO change is coincident to the SDO read at the falling edge of the SCLK. I had originally thought the default was that the SDO driven on the rising edge of SCLK, but this might be a consequence of having the SCLK idle high.
Instead of changing the FSDO setting, can you change the Saleae to read the device such that the data is read in at the rising edge? This is just to verify the correct data output. If the microcontroller is not reading the value correctly, then you may need to change the SCLK to idle low.
Joseph Wu
