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DAC38J82EVM: Compatibility with Xilinx ZCU102 or ZCU104

Juan Escobedo
Prodigy 40 points
Part Number: DAC38J82EVM

We want to evaluate the DAC38J82EVM and we have both a ZCU102 and ZCU104 however we are unsure if this will work since we see the SYNC pins on the EVM (F10 and F11) as well as the clock and SYSREF to the FPGA (J2/3 and K4/5 on the EVM) pins are not connected neither on the 102 or 104 FMC connectors. 

It seems this combo (or even the ZCU106) don't work at all or don't work straight out of the box: 

- https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/902641/dac38j84evm-tsw14j10-zcu106-with-jesd204-ti-reference-design-doesn-t-work

- https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1014759/dac39j82evm-support-for-xilinx-zynq-ultrascale-plus-evm-zcu106#:~:text=Part%20Number:%20DAC39J82EVM%20Hi%2C%20I%20was%20going,one%20of%20the%20forum%20posts%20@%20https://e2e.ti.com/support/data%2Dconverters%2Dgroup/data%2Dconverters/f/data%2Dconverters

Documentation seems to indicate the TSW14J10EVM adapter board could be required to make this work, https://www.ti.com/tool/TSW14J10EVM

Any insights would be appreciated.

  • 0
    TI__Mastermind 22060 points

    Hi Juan,

    Unfortunately it is not possible due to the SYNC not being connected and this device not offering a software register to act as SYNC signal. For your reference, the SYSREF comes on FMC pin G9/G10 and the MGT ref clock comes on pin D4/D5 and connects to clock capable pin on bank 229. The only problem is the lacking SYNC signal. Since there is no way to connect to this pin via a test point or header, it will not work as this device only supports subclass 1 mode. An interposer would be required to correct the mapping issue for this DAC EVM to work with the ZCU10x through the FMC.

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 40 points

    Hello Chase.

    Someone suggested using a SMA connector or PMOD on the ZCU102 to output the SYNC signal and connecting that to pin 1 of J21 of the DAC38J82EVM board.

    Would that work?

  • 0 in reply to Juan Escobedo
    TI__Mastermind 22060 points

    Hi Juan,

    If you are wanting to use CMOS sync, then yes that will work. Ensure field syncnab_ sel and syncncd_ sel in register 0x61 remains at value 0x0 each. In constraint file you will have to map sync to the corresponding new FPGA pins.

    Chase