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ADC09SJ1300: Questions of JESD204 protocol

Moon Wang
Intellectual 1040 points
Part Number: ADC09SJ1300

hi team,

My customer asked that which type the differential clock pin(CLK+, CLK-) from ADC09SJ1300 could be connected to, HR bank or HP bank of FPGA? And then, Does the JESD204C of ADC09SJ1300 need to apply the IP which in https://www.ti.com.cn/tool/cn/TI-JESD204-IP ? is it  necessary？ Many thanks for your help!

  • +1
    TI__Genius 15321 points

    Hi Moon,

    It is not recommended to use an FPGA to clock the ADC. The clocking requirements can be found in the datasheet on pg. 24. and the VID(DIFF) recommended ranges are in the datasheet on pg. 12. The IP is an optional framework for developing firmware in a capture solution. 

    Regards, Amy