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DAC3154: Would DACCLKP/N still work with LVDS like in DAC3152?

Danny R.
Prodigy 75 points
Part Number: DAC3154
Other Parts Discussed in Thread: DAC3152,

I'm comparing both DACs (DAC3152) & (DAC3154) and I'm trying to find, which one is more suitable for my design.

In datasheet for DAC3152 it's mentioned, that the preferred input clock consists of a differential ECL/PECL

I can't get this in the setup of my FPGA, so I'm going for the LVDS, that is also an option here.

Would this work too for the DAC3154? This isn't mentioned in the datasheet and I'm not sure, how to get it working like this. This is a list, of what the VC707 FPGA from Xilinx can set for I/Os.

Would there be an easy way to get the desired setup without any losses or disturbances?

  • 0
    TI__Mastermind 26570 points

    Hi Danny,

    LVDS will probably not work so good, it just above the threshold for sampling clock input. 1V differential is recommended.

    Also, using an FPGA is a poor clock choice if you plan to achieve near datasheet performance of the DAC.

    I would choose a clocking device and scheme with lower noise and higher slew.

    Regards,

    Rob