Hi,
When I enable test pattern and enable digital bypass, I can see the test pattern in my FPGA debugging environment.
But with bypass disabled. There is no test pattern anymore, just raw ADC data (same with test pattern off and digital bypass on).
Is it possible to use the test pattern with digital bypass disabled?
According to the datasheet figure 8-48 and also the ADC35XX EVM GUI graphs, this should be possible, but I see a different behaviour.
I'd appreciate any hints.