Dear Sirs,
in a new design we're using two ADC12DL3200 to acquire 3 RF input channels. The clock frequency
can be selected between 2 and 3 Ghz.
The first ADC has the INA and INB connected to RF input channels and the four data buses are connected to a FPGA.
The second ADC has only the INA connected to the RF input channel and only two data buses are connected to a FPGA.
To design only a one FW IP, I will manage the ADC12DL3200 with the same configuration. The two ADC will be
configured in DUAL CHANNEL mode and:
- in the first ADC, the A and C data buses will manage the INA samples and the B and D buses will
manage INB samples.
- in the second ADC, the A and C data buses will manage the INA samples while all the lines of B and D
buses that manage the INB input will be floating.
Do you think that the second ADC works correclty?
Do you think that I must terminated the 12+12+2 differential lines floating ?
Thanks in advance.
Best Regards,
Daniele
