ADS8345: ADS8345 Zero Crossing Issue

Hi Ismail,

I don't see the 'glitch' that you are talking about.  Can you please send a screen shot of the SPI control lines?  Can you capture /CS, SCLK, SDI and SDO at the controller versus the ADS8345?

please look at values and last real time plotting data, there is a jump at zero crossing point especially on low amplitude signals

Maybe the glitch is wrong name, at the zero crossing point values are not coming smoothly, I have been requesting the conversion values at 5khz sampling rate, input signal was 10 hz.

It is obvious I have passing more time at zero region in lower amplitude signals than the higher ones but why these zero transitions are not smooth ?

Even I sample the data ( this means I am sending read-conversion command and getting results at that rate) up to 100KHz, zero crossing is not proper.

For example, this data below sampled at 50khz, look at zero crossing there is a jump.

Hi Thomas,

OK - I can see you glitch here:

Where are you probing with the Saleae in that screen capture?  At the chip or at the controller side?

Look at the photo, Red lines are coming from the board where I soldered that cables to control ADC then I got two output which one is going to the controller, the other one is going to the logic analyzer.

The first photo below is taken from ADS8345EVM ADC conversion results which I did similar setup with evaluation board, the next one are the incoming data at production board.

Both signals was sine wave, 12.5 Hz, data are reading at 5khz, 1100-1250 Vpp.

Signal we sent from input and saw on the ADC channel is clean, we thought FPGA was the problem, erased the firmware of FPGA, and connected with another board as you see, but the problem is still persistent. It is becoming more apparent in lower amplitude which is unfortunately our frequency of interest.

Can you capture those signals with an oscilloscope?  Logic analyzers are nice, but they can't always see noise/glitches in the control lines.

These photos above belong to our board not STM32 evaluation setup.

Channel 2 Blue one is MISO ( Data output from ADC)

Yellow is SCK, Pink one is MOSI ( FPGA Command Output)

Hi Ismail,

Your SCLK is only reaching 2V which is not getting up to valid VIH levels.  MOSI still looks problematic as well - the two single bits in the middle transaction may not be reaching valid VIH levels.

Hi Tom,

I've made very interesting thing, I pulled out ADS8345N which is over one of unused our board, pulled out ADS8345E on the evaluation board either, then soldered ADS8345N to the evaluation board, which we proved everything is okay.

So I've made some test on evaluation board.

Results was interesting. I have used identical 12.5Hz sine wave 1100mV~ amplitude, and driven the ADC in INTERNAL CLOCK MODE. Whenever I change the SPI CLK, the zero crossing behavior was different. 

Results were not correct if SCL is very close to 2.4MHz which is internal clock, please see below

this is 2Mbit/s SCLK

4Mbit/s was better but there were some problems on zero crossing

6Mbit/s behaves like 4Mbits

8Mbit/s, zero crossing is very good.

I found 7.5 Mbit/s is the best.

If I change SPI CLK on our own board, it doesn't change anything on neither zero-crossing issue, nor zero crossing behavior.

I don't have an estimation about the reason, I can say something like noise etc. but it wouldn't be satisfying.

But you are true, the clock signal is very low, I don't know why.

How did you swap an 'E' device for an 'N' device?  One is TSSOP and the other is a QFN package, they are not pin compatible...

They are same SSOP20

Let's see if you can figure out the clock amplitude issue.  That is on your controller side.