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DAC7311: Overshoot on DAC output

Part Number: DAC7311

Hello,

My customer is seeing ~100mV of overshoot when changing the output code from 0V to 630mV. They have a 1µF cap on AVDD and a 47kΩ resistor from VOUT to ground. They asked if this is normal behavior and what can they do to minimize it. 

I noticed that the datasheet settling times both have a load capacitance and load resistance. Will adding capacitance help? Additionally, the command they are sending is: 1001 1100 0000 1011

Thanks in advance!

John

  • Hi John, 

    I'm checking this now and will get back to you shortly. 

    Best,

    Katlynne

  • Hi John, 

    The settling time plot does show an overshoot of ~200mV but for a larger code step than the customer is using:

    Adding a capacitor to the output would help this overshoot, just make sure the value is not larger than the capacitive load spec in the datasheet so the internal output buffer does not become unstable:

    Is 1001 1100 0000 1011 really the code they are sending? The first two bits are the power down bits and 10 would set the device to 100 kΩ to ground power down. 

    Best,

    Katlynne Jones 

  • I saw that with the first two bits and was trying to figure out how that was possible. I suggested trying to add a cap yesterday but will add your snippets to another reply. I will let you know when I know more. 

    John

  • Hi John, 

    To add to my response, the settling time figure from the datasheet is starting from a non-zero code. The extra overshoot could be coming from slew-boosting on the output as the amplifier is coming out of the negative rail (ground). 

    They can try setting the output to a lower code first, maybe 50mV and seeing if they see the same overshoot on the 50mV to 630mV transition. Let me know when you hear back. 

    Best,

    Katlynne