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TLC2574 Offset error condition

D. Johnson
Intellectual 700 points
Other Parts Discussed in Thread: REF3020, TLC2574, REF3040

We have a design that is using the TLC2574 in single ended mode.  We seem to be seeing a positive offset of ~ 50-100 mV on our expected readings at normal room temperatures. This relates to 10-20 ADC counts.  We are using the REF3040 (4.096) as the external reference.  As a test, we connected a single ended reference, REF3020, to one of the analog inputs.  The +50mV offset was also observed.  Signals being measured are DC like, very low if any frequency content.

Questions - 

1) Is an offset typical or an anomilly ?

2) Any thoughts on were this offset could be coming from ?

3) Using the internal test voltages, is there a suggested "calibration" process to result in more accurate readings ?

4) Datasheet has a max REFP of 4.04 V, while our design (and the TI EVM) uses a 4.096 Volts.  Could this be part of the offset issue ?

Thanks for the responses.

 

  • 0
    TI__Guru**** 168605 points

    Hi D. Johnson,

    There is some offset error inherent in the TLC2574 device, so the answer to your first question is that this is 'typical'.  The 4.096V reference will cause about ~50mV of offset which would then be added to any offset in the device itself.  If you take a look at the equivalent circuit on page 3 of the TLC2574 data sheet and crunch the numbers, you'll see that the divider ratio is optimized for 4.00V at REFP for a full scale input. 

    As a raw calibration of sorts, you can go in and subtract the offset error out from the conversion results, which essentially is going to reduce your dynamic range a little.  The internal self tests will use the 4.096V reference as well, so a more accurate means of calibrating would be to compare the applied voltage that generates the full scale code to the ideal of +10V.