ADS7038-Q1: Question about AVDD effect on SPI interface

Hi Tom

The concern is if we're using a common bus for SDI to multiple devices, would a drop on the AVDD power bus cause the SDI signal to be pulled low due to an ESD structure, or other mechanism.

Thanks,

Jim B

Hi Tom

I have a couple follow-up items for clarification:

The device without AVDD will go into reset, which is expected. In this condition, clocking SCLK while chip select is low (active) will result in garbage data, which is also expected. If chip select remains high (inactive) and AVDD drops out (chip in reset), is it correct to say that SDO will remain high impedance and not impact other devices being driven on the bus as long as DVDD remains powered?

Thanks for your response.

Jim B

Hi Tom,

The engineer would also be willing to hop on a call tomorrow or Monday if that works better for you.

Sure thing - my calendar is up to date.  I'm available from 7AM us central time.